Efficiency of crystalline Si solar cell can be maximized as minimizing optical loss through antireflection texturing with inverted pyramids. Even if cost-competitive, soft lithography can be employed instead of photolithography for the purpose, some limitations still remain to apply the soft lithography directly to as-received solar grade wafer with a bunch of micro trenches on surface. Therefore, it is needed to develop a low-cost, effective planarization process and evaluate its output to be applicable to patterning process with PDMS stamp. In this study new surface planarization process is proposed and the change of micro scale trenches on the surface as a function of etching time is observed. Also, the effect of trenches on pattern quality by soft lithography is investigated using FEM structural analysis. In conclusion it is clear that the geometry and shape of trenches would be basic considerations for soft lithography application to low quality wafer.

We design, develope and test a parallel active polymer pen lithography (PPL) device, which consists of individually addressable elastomeric probe tips. The PPL array chip is fabricated using soft lithography method with polydimethylsiloxane (PDMS) material. Individual probe can be pneumatically actuated via a computer controlled interface. We demonstrate parallel writing with 16 individually addressed pens, with each pen producing a different pattern in the same run. The largest proof-of-concept array fabricated is 4×4 with a spacing of 250 μm in both x and y axes.