Aggressive device scaling has severely degraded the switching characteristics of CMOS transistors. This issue has led to the development of tunneling FETs (TFETs) as an alternative. TFETs, with their asymmetric doping of the source and drain regions, offer improved subthreshold swing (SS) compared to conventional MOSFETs. However, despite this advantage, TFETs still suffer from ambipolar current, which increases off-state current (IOFF). This paper introduces an approach to applying hetero gate dielectrics (HGDs) in nanosheet (NS) TFETs to reduce ambipolar current characteristics. The magnitude of the drain electric field is reduced by selectively forming a high-k dielectric near the source region This configuration allows the TFETs to avoid unintended band-to-band tunneling (BTBT) and suppress ambipolar current during the off-state.

Various process modifications have been used to minimize SiO₂ gate oxide aging in metal-oxide-semiconductor field-effect transistors (MOSFETs). In particular, post-metallization annealing (PMA) with a deuterium ambient can effectively eliminate both bulk traps and interface traps in the gate oxide. However, even with the use of PMA, it remains difficult to prevent high levels of radiation-induced gate oxide damage such as total ionizing dose (TID) during long-term missions. In this context, additional low-temperature heat treatment (LTHT) is proposed to recover from radiation-induced damage. Positive traps in the damaged gate oxide can be neutralized using LTHT, thereby prolonging device reliability in harsh radioactive environments.

Thermal effects in bulk and SOI FinFETs are briefly reviewed herein. Different techniques to measure these thermal effects are studied in detail. Self-heating effects show a strong dependency on geometrical parameters of the device, thereby affecting the reliability and performance of FinFETs. Mobility degradation leads to 7% higher current in bulk FinFETs than in SOI FinFETs. The lower thermal conductivity of SiO2 and higher current densities due to a reduction in device dimensions are the potential reasons behind this degradation. A comparison of both bulk and SOI FinFETs shows that the thermal effects are more dominant in bulk FinFETs as they dissipate more heat because of their lower lattice temperature. However, these thermal effects can be minimized by integrating 2D materials along with high thermal conductive dielectrics into the FinFET device structure.

In this study, in order to develop the composition ceramics with the excellent electrocaloric properties, 8/65/35 PLZT ceramics were fabricated by the conventional solid-state method with the addition of Bi2O3, CuO, Li2CO3 and the variation of sintering temperature from 930℃ to 990℃. The XRD pattern of all specimens indicated general perovskite structure and the rhombohedral phase were observed. Curie temperature (Tc) of all specimens was observed in the vicinity of about 190℃. Density, coercive field and remnant polarization of the specimen sintered at 950℃ was 7.55 g/cm3, 8.895 kV/cm, 11.22 μC/㎠, respectively. EC effect of PLZT ceramics was measured by indirect method and the temperature change ΔT due to the electrocaloric effect was calculated by Maxwell’s relations. ΔT of ceramic sintered at 950℃ was 0.21℃ under application of 40 kV/cm at 190℃.

In this study, in order to develop the composition ceramics with the excellent electrocaloric properties, (Pb0.88La0. 08)(Zr0.65Ti0.35)O3 ceramics were fabricated by the conventional solid-state method. Electrocaloric effects of (Pb0.88La0.08)(Zr 0.65Ti0.35)O3 ferroelectric ceramics were investigated and discussed using the characteristics of P-E hysteresis loops at wide temperature range from room temperature to 220 . The temperature change ΔT due to the electrocaloric effec t was calculated by Maxwell’s relations, and reached the maximum of 0.19 at 190 under applied electric field of 30 kV/cm.