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낮은 온저항과 칩 효율화를 위한 Unified Trench Gate Power MOSFET의 설계에 관한 연구

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Design of Unified Trench Gate Power MOSFET for Low on Resistance and Chip Efficiency

Ey Goo Kang
J Electr Electron Mater 2013;26(10):713-719.
Published online: October 1, 2013
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Power MOSFET operate voltage-driven devices, design to control the large power switching device for power supply, converter, motor control, etc. We have optimal designed planar and trench gate power MOSFET for high breakdown voltage and low on resistance. When we have designed 6,580 um ×5,680 um of chip size and 20 A current, on resistance of trench gate power MOSFET was low than planar gate power MOSFET. The on state voltage of trench gate power MOSFET was improved from 4.35 V to 3.7 V. At the same time, we have designed unified field limit ring for trench gate power MOFET. It is Junction Termination Edge type. As a result, we have obtained chip shrink effect and low on resistance because conventional field limit ring was convert to unify.

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Design of Unified Trench Gate Power MOSFET for Low on Resistance and Chip Efficiency
J Electr Electron Mater. 2013;26(10):713-719.   Published online October 1, 2013
Download Citation

Download a citation file in RIS format that can be imported by all major citation management software, including EndNote, ProCite, RefWorks, and Reference Manager.

Format:
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Design of Unified Trench Gate Power MOSFET for Low on Resistance and Chip Efficiency
J Electr Electron Mater. 2013;26(10):713-719.   Published online October 1, 2013
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