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J Electr Electron Mater : Journal of Electrical and Electronic Materials

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진공 게이트 스페이서를 지니는 Bulk FinFET의 단채널효과 억제를 위한 소자구조 최적화 연구

연지영, 이광선, 윤성수, 연주원, 배학열, 박준영

Device Optimization for Suppression of Short-Channel Effects in Bulk FinFET with Vacuum Gate Spacer

Ji-yeong Yeon, Khwang-sun Lee, Sung-su Yoon, Ju-won Yeon, Hagyoul Bae, Jun-young Park
J Electr Electron Mater 2022;35(6):576-580.
Published online: November 1, 2022
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Semiconductor devices have evolved from 2D planar FETs to 3D bulk FinFETs, with aggressive device scaling. Bulk FinFETs make it possible to suppress short-channel effects. In addition, the use of low-k dielectric materials as a vacuum gate spacer have been suggested to improve the AC characteristics of the bulk FinFET. However, although the vacuum gate spacer is effective, correlation between the vacuum gate spacer and the short-channel-effects have not yet been compared or discussed. Using a 3D TCAD simulator, this paper demonstrates how to optimize bulk FinFETs including a vacuum gate spacer and to suppress short-channel effects.

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Device Optimization for Suppression of Short-Channel Effects in Bulk FinFET with Vacuum Gate Spacer
J Electr Electron Mater. 2022;35(6):576-580.   Published online November 1, 2022
Download Citation

Download a citation file in RIS format that can be imported by all major citation management software, including EndNote, ProCite, RefWorks, and Reference Manager.

Format:
Include:
Device Optimization for Suppression of Short-Channel Effects in Bulk FinFET with Vacuum Gate Spacer
J Electr Electron Mater. 2022;35(6):576-580.   Published online November 1, 2022
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