In parallel with the efforts to improve the device performance in modern integrated circuits, it is necessary to downscale their core components, field-effect transistors (FETs), generally gauged by their physical gate length. Upon such device scaling, the emergence of the short-channel effect impedes further scaling into the nanometer scale in the silicon VLSI (Very-Large-Scale-Integration) system. To address this issue, two-dimensional (2D) semiconductors, leveraging their atomically thin thickness and dangling-bond-free characteristics, are being highlighted as a material solution for future scaling technology without severe mobility degradation. Despite the expected ideal physical properties, 2D semiconductors have yet to realize their full potential owing to the limited development of integration technology. In this context, we survey and review the tailored van der Waals integration technologies for 2D FETs. In particular, we provide an in-depth study of both van der Waals integrated contact and dielectric methods along with an explanation of customized materials. In essence, this van der Waals integrationcentered approach will be a core strategy to implement the high-performance 2D transistors that meet the demand of FET miniaturization.

This review examines the principles, limitations, and recent advancements in elastic modulus measurement using nanoindentation. The importance of accurate contact area prediction is discussed, along with the Oliver-Pharr method and its limitations. The Continuous Stiffness Measurement (CSM) technique is presented as a significant improvement, allowing continuous measurement of mechanical properties throughout the indentation process. For ultra-thin films, the Li and Vlassak method, which incorporates Yu's solution and the concept of effective thickness, is highlighted as a means to correct for substrate effects. Recent developments in artificial neural network-based models for elastic modulus prediction are also explored. These advancements have greatly expanded the applicability of nanoindentation in semiconductor and MEMS device reliability assessment.

Ceramic powder is an important material used for various purposes in advanced industries, and the fundamental properties of ceramic powder such as particle size, particle size distribution, and flow properties play a decisive role in determining the quality and performance of the final product. In general, these properties have been evaluated through particle size and shape analysis. However, these methods have limitations in providing a comprehensive understanding phenomena related to powder flow, coagulation, and wear. Consequently, performance evaluation based on the analysis of powder flow properties has been increasingly adopted. Previously, flow properties were primarily assessed using funnel-based methods. However, these methods have limitations, as they are challenging to apply to powders smaller than a few micrometers or those with strong coagulation tendencies, and they also suffer from low reliability. To address these issues, this paper introduces a novel piece of equipment that measures flow properties using image analysis and presents various parameters for static and dynamic flow behavior based on this technique. The proposed equipment offers exceptional versatility, as it can be applied to all types of ceramic powders regardless of their size or shape. The principles and measurement methods of the equipment are demonstrated through static and dynamic image analysis of ceramic powders with varying sizes and shapes used as examples.

Recently, oxide semiconductors have assumed a pivotal role in electronic displays and transparent electronic devices such as amorphous indium gallium zinc oxide (a-IGZO), characterized by high electron mobility and excellent stability. a- IGZO is very suitable for next-generation applications such as flexible displays because it is possible to manufacture highperformance transistors even at low temperatures. However, since the electrical properties tend to deteriorate in hightemperature environments, research aimed at improving thermal stability is needed. In this study, a low-temperature plasma annealing process was introduced to improve the high-temperature stability of the a-IGZO thin film. This process enhances electron mobility by reducing defects in the a-IGZO film and provides stable device performance even under high-temperature conditions. As a result of the experiments of 5 min, 10 min, 15 min, and 20 min, the a-IGZO TFT, which was subjected to plasma annealing at 160℃ for 5 min, showed the best electrical performance, especially in charge mobility and current-voltage characteristics. The technical potential for improving the performance of a-IGZO-based display device was emphasized, and the foundation for applying this power generation to flexible displays and next-generation electronic devices was laid. Future research will focus on determining the optimal annealing conditions by exploring various temperature ranges and plasma parameters to integrate these results into the actual device manufacturing process. These efforts are expected advance significantly to advancing next-generation high-performance display technology.

SMD-type 660 nm wavelength semiconductor laser diode device is fabricated using silicon resin molding technology and fabricated a BT resin printed circuit board. BT resin electrode structure printed circuit boards with soldering electrode pads and through holes for heat dissipation were fabricated. The SMD process is an injection molding technique in which the chip is molded from silicon material and then cut by a dicing process to complete the beam emission surface. The fabricated SMD-type semiconductor laser diode exhibits a good near-field beam pattern with no scattering/dispersion caused by the printed circuit board or silicon molding in the emitted laser beam, or reflections around the chip. It was also confirmed that the heat generated at 20 mA operation has good heat dissipation characteristics through the through-hole heat dissipation structure.

We have proposed and demonstrated a fiber optic magnetic field sensor using a FBG (fiber bragg grating) attached on a Terfenol-D bar. The volume of Terfenol-D is changed by the applied magnetic field due to the magnetostriction effect, as a result, the grating period of FBG varies with the intensity of the magnetic field and the Bragg wavelength of FBG is shifted. The temperature sensitivity of the sensor was measured with and without the magnetic field. The temperature sensitivity of the sensor was measured to be 0.02 nm/℃. We observed that the sensitivity of the fabricated device to magnetic field intensity was decreased with the environment temperature.

This study aimed to elucidate factors limiting power conversion efficiency (PCE) in GaN-based micro-light-emitting diodes (μ-LEDs). To this end, we investigated the effects of operating temperature and chip-size of μ-LEDs on their efficiency. For the investigation, 460 nm-emitting μ-LEDs with various chip-sizes were fabricated; then their characteristics were carefully measured from 100 to 400 K. As the chip-size decreases and the operating temperature increases, their PCE and external quantum efficiency (EQE) decrease, while voltage efficiency (VE) increases. This indicates that the EQE plays a more important role than the VE in determining the PCE of μ-LEDs. Particularly, for a chip-size of 20 × 20 μm², the EQE was very lower and the ideality factor was unexpectedly higher compared to the others for all operating temperatures, which is believed to be due to the critical plasma damage at the sidewall during dry-etching process for the chip-size < 20 × 20 μm².

The characteristics of each address discharge were investigated when the voltages of the scan and common electrodes were lowered simultaneously during an address period under the same address voltage conditions in an AC plasma display panel. It was confirmed that the delay time of address discharge shortened as the voltage decreased. However, the background light increased because the low scanning voltage generated more discharge between the electrodes of the upper and lower plates in the reset period. To lower the background light, a positive voltage was applied to the address electrode of the lower panel during the period when the rising ramp wave was applied, and a floating voltage was applied to the address electrode during the period when the falling ramp wave was applied during the reset period. As a result, the background light could be lowered by about 30%.

Aggressive device scaling has severely degraded the switching characteristics of CMOS transistors. This issue has led to the development of tunneling FETs (TFETs) as an alternative. TFETs, with their asymmetric doping of the source and drain regions, offer improved subthreshold swing (SS) compared to conventional MOSFETs. However, despite this advantage, TFETs still suffer from ambipolar current, which increases off-state current (IOFF). This paper introduces an approach to applying hetero gate dielectrics (HGDs) in nanosheet (NS) TFETs to reduce ambipolar current characteristics. The magnitude of the drain electric field is reduced by selectively forming a high-k dielectric near the source region This configuration allows the TFETs to avoid unintended band-to-band tunneling (BTBT) and suppress ambipolar current during the off-state.

Next-generation display technologies, including rollable and foldable displays, are advancing rapidly, enabling innovative and versatile form factors. Flexible displays predominantly utilize materials such as Polyimide (PI), Colorless Polyimide (CPI), and Thermoplastic PolyUrethane (TPU) due to their exceptional flexibility and durability. However, a significant challenge lies in the lack of standardized criteria for evaluating the durability of these flexible substrates. In this study, the durability of these materials under rolling conditions was investigated. This study establishes a standardized methodology for evaluating flexible materials used in rollable displays. Experiments were performed on PI, including rolling and scratch tests with varying indenter sizes. Friction data from the scratch tests, combined with cross-sectional analyses, were examined using optical microscopy and Scanning Electron Microscopy (SEM). The scratch test results revealed that PI films with lower elastic recovery exhibited distinct damage patterns during rolling cycles, especially when smaller indenter radius were used. As the number of rolling cycles increased, the critical force decreased rapidly. This behavior was attributed to the weakening or breaking of atomic bonds within the film. This was further confirmed by SEM images, which revealed delamination of the film from the surface after rolling.

The quench behavior of coated conductors (CCs) was simulated with a focus on the initial stage of quenches, and the current limiting behavior of superconducting fault current limiters (SFCLs) at DC faults was calculated. Since the fault current reaches the peak in several ms in DC lines due to capacitor discharge, it is necessary to understand the initial quench behavior well. Considered in the simulation are characteristics of CCs in the flux-flow state, current sharing, non-uniform critical current distribution in CCs, and heat transfer to surroundings. The simulation fit data well. Using the CC model developed in the simulation, the current limiting behavior of SFCLs made of CCs at DC faults was calculated. Critical current distribution and heat transfer were found to affect the current limiting behavior of SFCLs less at DC faults. The calculation will contribute to the effective design of SFCLs for applications in DC lines.

The growing demand for miniaturized, lightweight, and sustainable electronic devices has intensified the need for advanced bonding materials. Existing electrically conductive adhesives (ECAs) often rely on high silver (Ag) content, resulting in elevated costs and environmental concerns. This study successfully developed a novel ECA with significantly reduced Ag content without compromising essential electrical conductivity and adhesion performance. Experimental results revealed that the optimized ECA demonstrates electrical conductivity comparable to that of commercial products, with notable advantages in cost reduction and eco-friendliness. These advancements position the developed ECA as a promising solution for next-generation electronic manufacturing, contributing to low-carbon technologies and sustainable practices. Future applications could further broaden its use across diverse electronic systems, driving progress in environmentally conscious technologies.

With the extensive industrial growth driven by the Fourth Industrial Revolution and the excessive use of fossil fuels, greenhouse gas emissions have accelerated global warming. Energy harvesting technologies have garnered significant attention as a potential solution to this issue. Among them, triboelectric nanogenerators (TENGs) have emerged as promising candidates for energy collection and conversion. However, TENGs typically face limitations in providing an efficient energy supply due to their high output voltage and low output current. To overcome these challenges, numerous studies have explored various methods to enhance the output performance by increasing the surface area of the triboelectric materials. Herein, we report a high-output TENG fabricated through a simple scratch process. By utilizing sandpaper, typically used for abrasion or polishing, the surface roughness of the triboelectric material PFA was increased through surface scratching. The surface-engineered TENG, prepared through this simple and rapid process, demonstrated enhanced output characteristics with a voltage of 276 V and a current of 72 μA, showing a 21% increase in voltage and a 41% increase in current compared to the non-engineered counterpart, providing sufficient energy to power an LED. These results indicate that the scratch-based surface modification process using sandpaper offers an effective solution for improving triboelectric output performance, establishing TENGs as a key contributor to sustainable energy supply.

The solution-based fabrication process for resistive random-access memory (ReRAM) offers several advantages over conventional vapor deposition processes, including simplicity, cost-effectiveness, and high versatility for coating complex structures over large areas. In this study, a TiO₂-based ReRAM device was fabricated using a solution process with Pt top and P⁺⁺-Si bottom electrodes. The synthesized TiO₂ films contain a residual Cl element as revealed by X-ray photoelectron spectroscopy (XPS). Reversible volatile resistance switching was observed due to the formation of conductive Ti-O-Ti networks in the TiO₂ layer. Post-annealing led to an increase in the threshold voltage (Vth). Asymmetric Current-Voltage characteristics was observed due to the different in the work functions of the electrodes. Additionally, the influence of compliance current settings on filament formation and hysteresis behavior was systematically investigated. The results demonstrated that higher compliance currents enhanced the hysteresis width for both positive and negative voltage bias conditions.

Neuromorphic computing, inspired by the biological mechanisms of neural signal transmission, has emerged as a promising technology for efficient and parallel data processing with minimal power consumption. In this study, we developed floating-gate organic thin-film transistors (OTFTs) with self-assembled monolayer (SAM)-based tunneling layers to mimic the characteristics of artificial synapses. The tunneling layers were formed using mixed phosphonic acid SAMs with varying ratios of octadecylphosphonic acid (ODPA) and 12-pentafluorophenoxydodecylphosphonic acid (PFPA). The influence of these ratios on the memory and neuromorphic characteristics of the devices was systematically evaluated. Our results revealed that the ODPA ratio significantly impacts the hysteresis window, with higher ODPA content yielding improved memory characteristics. Conversely, the PFPA : ODPA ratio of 2:1 exhibited the lowest non-linearity (NL = 0.48), demonstrating the potential for highly accurate weight updates in neuromorphic devices. Additionally, pulse width modulation studies showed that a pulse width of 100 ms optimized the linearity and stability of long-term potentiation (LTP) and depression (LTD) characteristics. The combination of sol-gel processed AlOx as a floating-gate layer and tailored SAM-based tunneling layers allowed for precise control of device performance. These findings highlight the importance of molecular engineering in designing SAM layers to balance memory retention and neuromorphic functionality. This study provides a pathway for advancing organic floating-gate transistors as a core component in next-generation neuromorphic computing systems.