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"NAND flash memory"

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"NAND flash memory"

Electro-Thermal Annealing of 3D NAND Flash Memory Using Through-Silicon Via for Improved Heat Distribution
Young-seo Son, Khwang-sun Lee, Yu-jin Kim, Jun-young Park
J Korean Inst Electr Electron Mater Eng 2023;36(1):23-28.   Published online January 1, 2023
DOI: https://doi.org/10.4313/JKEM.2023.36.1.4
This paper demonstrates a novel NAND flash memory structure and annealing configuration including through-silicon via (TSV) inside the silicon substrate to improve annealing efficiency using an electro-thermal annealing (ETA) technique. Compared with the conventional ETA which utilizes WL-to-WL current flow, the proposed annealing method has a higher annealing temperature as well as more uniform heat distribution, because of thermal isolation on the silicon substrate. In addition, it was found that the annealing temperature is related to the electrical and thermal conductivity of the TSV materials. As a result, it is possible to improve the reliability of NAND flash memory. All the results are discussed based on 3-dimensional (3-D) simulations with the aid of the COMSOL simulator.
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The Characteristics of p-channel SONOS Transistor for the NAND Charge-trap Flash Memory
Byung Cheul Kim, Joo Yeon Kim
J Korean Inst Electr Electron Mater Eng 2009;22(1):7-11.   Published online January 1, 2009
DOI: https://doi.org/10.4313/JKEM.2009.22.1.007
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Trap Generation Analysis by Program/Erase Speed Measurements in 50nm Nand Flash Memory
Byoung Taek Kim, Yong Seok Kim, Sung Hoi Hur, Jang Min Yoo, Yong Han Roh
J Korean Inst Electr Electron Mater Eng 2008;21(4):300-304.   Published online April 1, 2008
DOI: https://doi.org/10.4313/JKEM.2008.21.4.300
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