Silicon carbide (SiC) power devices are attracting increasing attention for high-voltage and high-efficiency applications due to their superior material properties. However, achieving an optimal trade-off between specific on-resistance (Ron,sp) and breakdown voltage (BV) remains a key design challenge in planar MOSFET structures. In this study, twodimensional TCAD simulations were conducted to investigate the impact of varying the doping concentrations of the P-well (from 3 × 10¹⁷ to 6 × 10¹⁷ cm^-3) and JFET regions (from 1 × 10¹⁶ to 7 × 1016 cm^-3) on the electrical characteristics of 2.4 kVclass planar SiC MOSFETs. To maintain comparable BV conditions for 2.4 kV operation, two groups with P-well doping concentrations of 4.5 × 10¹⁷ cm^-3 and 5.3 × 1017 cm^-3 were analyzed and compared. When the P-well and JFET doping concentrations were 4.5 × 10¹⁷ cm^-3 and 1.5 × 10¹⁶ cm^-3, respectively, the simulated Ron,sp and BV were 1.41 mΩ·cm² and 3,150 V. In contrast, with P-well and JFET doping concentrations of 5.3 × 10¹⁷ cm^-3 and 5.0 × 10¹⁶ cm^-3, the Ron,sp was reduced to 1.31 mΩ·cm² while the BV slightly increased to 3,200 V. Based on these results, an optimized device structure was proposed, demonstrating its potential for integration into high-voltage SiC-based power systems. This study provides practical design insights and is expected to contribute to the advancement of wide bandgap semiconductor technologies for next-generation power electronics.

This reports the electrical properties of single-crystal β-gallium oxide (β-Ga₂O₃) vertical Schottky barrier diodes (SBDs) with a different guard ring structure. The vertical Schottky barrier diodes (V-SBDs) were fabricated with two types guard ring structures, one is with metal deposited on the Al₂O₃ passivation layer (film guard ring: FGR) and the other is with vias formed in the Al₂O₃ passivation layer to allow the metal to contact the Ga₂O₃ surface (metal guard ring: MGR). The forward current values of FGR and MGR V-SBD are 955 mA and 666 mA at 9 V, respectively, and the specific on-resistance (Ron,sp) is 5.9 mΩ·cm² and 29 mΩ·cm². The series resistance (Rs) in the nonlinear section extracted using Cheung’s formula was 6 Ω, 4.8 Ω for FGR V-SBD, 10.7 Ω, 6.7 Ω for MGR V-SBD, respectively, and the breakdown voltage was 528 V for FGR V-SBD and 358 V for MGR V-SBD. Degradation of electrical characteristics of the MGR V-SBD can be attributed to the increased reverse leakage current caused by the guard ring structure, and it is expected that the electrical performance can be improved by preventing premature leakage current when an appropriate reverse voltage is applied to the guard ring area. On the other hand, FGR V-SBD shows overall better electrical properties than MGR V-SBD because Al₂O₃ was widely deposited on the Ga₂O₃ surface, which prevent leakage current on the Ga₂O₃ surface.

This report constitutes the first demonstration in Korea of single-crystal lateral gallium oxide (Ga₂O₃) as a metal-oxide-semiconductor field-effect-transistor (MOSFET), with a breakdown voltage in excess of 480 V. A Si-doped channel layer was grown on a Fe-doped semi-insulating β-Ga₂O₃ (010) substrate by molecular beam epitaxy. The single-crystal substrate was grown by the edge-defined film-fed growth method and wafered to a size of 10×15 mm². Although we fabricated several types of power devices using the same process, we only report the characterization of a finger-type MOSFET with a gate length (L_g) of 2 μm and a gate-drain spacing (L_gd) of 5 μm. The MOSFET showed a favorable drain current modulation according to the gate voltage swing. A complete drain current pinch-off feature was also obtained for V_gs<-6 V, and the three-terminal off-state breakdown voltage was over 482 V in a L_gd＝5 μm device measured in Fluorinert ambient at V_gs＝-10 V. A low drain leakage current of 4.7 nA at the off-state led to a high on/off drain current ratio of approximately 5.3×10⁵. These device characteristics indicate the promising potential of Ga₂O₃-based electrical devices for next-generation high-power device applications, such as electrical autonomous vehicles, railroads, photovoltaics, renewable energy, and industry.

In this work, static characteristics of 4H-SiC SJ-ACCUFETs were obtained by adjusting the p-pillar region. The structure of this SJ-ACCUFET was designed by using a two-dimensional simulator. The static characteristics of SJ-ACCUFET, such as the breakdown voltages, on-resistance, and figure of merits, were obtained by varying the p-pillar doping concentration from 1×10¹⁵ cm^-3 to 5×10¹⁶ cm^-3 and the thickness from 0 μm to 9 μm. The doping concentration and the thickness of p-pillar region are closely related to the break down voltage and on-resistance and threshold voltages. Hence a silicon carbide SJ-ACCUFET structure with highly intensified breakdown voltages and low on-resistances with good figure of merits can be achieved by optimizing the p-pillar thickness and doping concentration.

In this paper, we analyzed the electrical characteristics of NPT planar and trench gate IGBT after designing these devices according to design and process parameter. To begin with, we have designed NPT planar gate IGBT and carried out simulation with T-CAD. Therefore, we extracted design and process parameter and obtained optimal electrical characteristics. The breakdown voltage was 724 V and The on state voltage drop was 1.746 V. The next was carried out optimal design of trench gate power IGBT. We did this research by same drift thickness and resistivity of planar gate power IGBT. As a result of experiment, we obtain 720 V breakdown voltage, 1.32 V on state voltage drop and 4.077 V threshold voltage. These results were improved performance and fabrication of trench gate power IGBT and planar gate Power IGBT.

This paper was proposed floating island power MOSFET for lowering on state resistance and the proposed device was maintained 600 V breakdown voltage. The electrical field distribution of floating island power MOSFET was dispersed to floating island between P-base and N-drift. Therefore, we designed higher doping concentration of drift region than doping concentration of planar type power MOSFET. And so we obtain the lower on resistance than on resistance of planar type power MOSFET. We needed the higher doping concentration of floating island than doping concentration of drift region and needed width and depth of floating island for formation of floating island region. We obtained the optimal parameters. The depth of floating island was 32 ㎛. The doping concentration of floating island was 5 × 1,012 ㎠. And the width of floating island was 3 ㎛. As a result of designing the floating island power MOSFET, we obtained 723 V breakdown voltage and 0.108 Ω㎠ on resistance. When we compared to planar power MOSFET, the on resistance was lowered 24.5% than its of planar power MOSFET. The proposed device will be used to electrical vehicle and renewable industry.

This research was designed 700 level power MOSFET for smart LED driver ICs package. And we analyzed electrical characteristics of the power MOSFET as like breakdown voltage, on-resistance and threshold voltage. Because this research is important optimal design for smart LED ICs package, we designed power MOSFET with design and process parameter. As a result of this research, we obtained 60㎛ N-drift layer depth, 791.29 V breakdown voltage, 0.248 Ω·cm2 on resistance and 3.495 V threshold voltage. We will use effectively this device for smart LED driver ICs package

Power MOSFETs (metal oxide semiconductor field effect transistor) operate as energy control semiconductor switches. In order to reduce energy loss of the device during switch-on state, it is essential to increase its conductance. In this study we have investigated a structure to reduce the on-resistance characteristics of the MOSFET. We have a proposed MOSFET structure of active cells region buried under the gate pad. The measurement are carried out with a EDS to analyze electrical characteristics, and the proposed MOSFET are compared with the conventional MOSFET. The result of proposed MOSFET was 1.68[Ω], showing 10% improvement compared to the conventional MOSFET at 700[V].

Device model parameters are very important for accurate estimation of electrical performances in devices, integrated circuits and their systems. There are a large number of methods for extraction of model parameters in power MOSFETs. For high efficiency, design is important considerations of a power MOSFET with high-voltage applications in consumer electronics. Meanwhile, it was proposed that the efficiency of a MOSFET can be enhanced by conducting JFET region double implant to reduce the On-resistance of the transistor. This paper reports the effects of JFET region double implant on the electrical properties and the decreasing On-resistance of the MOSFET. Experimental results show that the 1st JFET region implant diffuse can enhance the On-resistance by decreasing the ion concentration due to the surface and reduce the On-resistance by implanting the 2nd Phosphorus to the surface JFET region.

This paper was analyzed electrical characteristics of super junction power MOSFETconsidering to charge imbalance. We extracted optimal design and process parameter at -15% of chargeimbalance. Considering extracted design and process parameters, we fabricated super junction MOSFETand analyzed electrical characteristics. We obtained 600∼650 V breakdown voltage, 224∼240 mΩ onresistance. This paper was showed superior on resistance of super junction MOSFET. We can use forautomobile industry.

Citations

• A Study on Optimization of Planar Gate Type Metal-Oxide-Semiconductor Field-Effect-Transistors Multi Epitaxial Process in Super-Junction Structure
  Chang Hyeon Jo, Dea Hee Kim, Hyeong Seong Jo, O Yong Kwon, Ey Goo Kang
  Journal of Nanoelectronics and Optoelectronics.2021; 16(5): 738.     CrossRef

This paper was showed latch up characteristics of super junction power MOSFET by parasiticthyristor according to trench etch angle. As a result of research, if trench etch angle of super junction MOSFET is larger, we obtained large latch up voltage. When trench etch angle was 90°, latch up voltage was more 50 V. and we got 700 V breakdown voltage. But we analyzed on resistance. if trench etch angle of super junction MOSFET is larger, we obtained high on resistance. Therefore, we need optimal point by simulation and experiment for solution of trade off.

This paper was developed and described core-process to implement low on resistance whichwas the most important characteristics of SJ (super junction) MOSFET. Firstly, using process-simulation,SJ MOSFET optimal structure was set and developed its process flow chart by repeated simulation. Following process flow, gate level process was performed. And source and drain level process wassimilar to genral planar MOSFET, so the process was the same as the general planar MOSFET. Andthen to develop deep trench process which was main process of the whole process, after finishing photomask process, we developed deep trench process. We expected that developed process was necessary todevelop SJ MOSFET for automobile semiconductor.

In this paper, we analyze electrical characteristics of n/p-pillar layer according to trench anglewhich is the most important characteristics of SJ MOSFET and core process. Because research target is600 V class SJ MOSFET, so conclusively trench angle deduced 89.5 degree to implement the breakdownvoltage 750 V with 30% margin rate. we found that on resistance is 22 mohm·cm2 and threshold voltageis 3.5 V. Moreover, depletion layer of electric field distribution also uniformly distributes.

Power MOSFET and Power IGBT is develop in power savings, high efficiency, small size, high reliability, fast switching, low noise. Power MOSFET can be used high-speed switching transistors devices. Power MOSFET is devices the voltage-driven approach switching devices are design to handle on large power, power supplies, converters. In this paper, design the 80V MOSFET Planar Gate type, and design the Trench Gate type for realization of low on-resistance. For both structures, by comparing and analyzing the results of the simulation and characterization.

In this work, we investigated the static characteristics of 4H-SiC vertical metal-oxide- semiconductor field effect transistors (VMOSFETs) by adjusting the doping level of n-epilayer and the effect of a current spreading layer (CSL), which was inserted below the p-base region with highly doped n+ state (5 x 1017 cm-3). The structure of SiC VMOSFET was designed by using a 2-dimensional device simulator (ATLAS, Silvaco Inc.). By varying the n-epilayer doping concentration from 1×1016 cm-3 to 1×1017 cm-3, we investigated the static characteristics of SiC VMOSFETs such as blocking voltages and on-resistances. We found that CSL helps distribute the electron flow more uniformly, minimizing current crowding at the top of the drift region and reducing the drift layer resistance. For that reason, silicon carbide VMOSFET structures of highly intensified blocking voltages with good figures of merit can be achieved by adjusting CSL and doping level of n-epilayer.