There is an increasing demand for freeform stretchable display technologies capable of overcoming spatial limitations in next-generation platforms such as augmented reality (AR) and virtual reality (VR). To realize such stretchable displays, all constituent materials—including semiconductors, electrodes, insulators, and substrates—must exhibit sufficient mechanical elasticity. To date, stretchable gate insulators have primarily relied on organic polymers such as poly(4-vinylphenol-co-methyl methacrylate) (PVP-co-PMMA). However, their practical application is significantly limited by poor electrical properties, including low dielectric constant and instability. In this work, we propose a novel gate insulator structure that minimizes the use of solution-based processes, which often suffer from poor uniformity and may damage underlying layers during fabrication. The proposed structure integrates the advantages of both organic and inorganic materials by employing a hybrid configuration. Specifically, high-k HfO₂ thin films are deposited on both the top and bottom of an organic layer composed of PVP-co-PMMA, poly(melamine-co-formaldehyde) (PMF) as a crosslinking agent, and propylene glycol monomethyl ether acetate (PGMEA) as a solvent. This inorganic–organic–inorganic structure effectively compensates for the inherent electrical limitations of organic materials. As a result, the fabricated thin-film transistors (TFTs) exhibit improved electrical performance and reliability compared to devices employing a single organic gate insulator.

This study investigates the effect of dielectric layer thickness on the electrical and reliability characteristics of BaTiO₃- based X8R multilayer ceramic capacitors (MLCCs) for automotive applications. MLCCs with 30 dielectric layers and thicknesses ranging from 5 to 30 μm were fabricated, and key parameters―including capacitance, equivalent series resistance (ESR), insulation resistance (IR), breakdown voltage (BDV), DC-bias characteristics, temperature coefficient of capacitance (TCC), and ripple current-induced heating―were evaluated. The dielectric constant (~2,000) and sintering shrinkage (~-25%) were nearly independent of thickness, confirming stable microstructure formation. ESR increased with thickness, while normalized BDV (V/μm) decreased due to defect accumulation. IR improved with increasing thickness but dropped sharply above 125℃. Dielectrics thinner than 10 μm exhibited significant capacitance degradation under DC-bias and temperature variation, reflecting strong internal field effects. Ripple-induced heating correlated directly with ESR. These results indicate that, although thinner layers enhance capacitance density, reducing the thickness below 10 μm compromises bias stability and thermal reliability. A minimum dielectric thickness of 10 μm is therefore recommended to achieve an optimal balance between electrical performance and durability in high-reliability X8R MLCCs.

This study investigates the effect of mask material and thickness on the silicon etching profile using a high-density plasma (HDP) etching system, aiming to reduce optical loss in silicon-based optical waveguides. As the mask thickness increased, the etching sidewall angle became steeper. An etching profile angle of 87° was obtained when tetraethyl orthosilicate (TEOS) was used as the mask material, while 80° was obtained for photoresist (PR). This is attributed to electron charging on the mask surface in the plasma. The charged mask modifies the distribution and strength of the electric field depending on its thickness, thereby affecting the trajectory of positive ions accelerated toward the substrate by the bias voltage. Furthermore, Plasma diagnostics using optical emission spectroscopy (OES) and surface composition analysis using field emission Auger electron spectroscopy (FE-AES) revealed that changes in the mask material also alter the reaction pathways and formation characteristics of active species and silicon by-products in the plasma. These results suggest that the mask material influences the overall plasma characteristics, including electron density and ion energy, and plays a critical role in the precise control of silicon etching profiles for high-performance optical device fabrication.

Silicon carbide (SiC) power devices are attracting increasing attention for high-voltage and high-efficiency applications due to their superior material properties. However, achieving an optimal trade-off between specific on-resistance (Ron,sp) and breakdown voltage (BV) remains a key design challenge in planar MOSFET structures. In this study, twodimensional TCAD simulations were conducted to investigate the impact of varying the doping concentrations of the P-well (from 3 × 10¹⁷ to 6 × 10¹⁷ cm^-3) and JFET regions (from 1 × 10¹⁶ to 7 × 1016 cm^-3) on the electrical characteristics of 2.4 kVclass planar SiC MOSFETs. To maintain comparable BV conditions for 2.4 kV operation, two groups with P-well doping concentrations of 4.5 × 10¹⁷ cm^-3 and 5.3 × 1017 cm^-3 were analyzed and compared. When the P-well and JFET doping concentrations were 4.5 × 10¹⁷ cm^-3 and 1.5 × 10¹⁶ cm^-3, respectively, the simulated Ron,sp and BV were 1.41 mΩ·cm² and 3,150 V. In contrast, with P-well and JFET doping concentrations of 5.3 × 10¹⁷ cm^-3 and 5.0 × 10¹⁶ cm^-3, the Ron,sp was reduced to 1.31 mΩ·cm² while the BV slightly increased to 3,200 V. Based on these results, an optimized device structure was proposed, demonstrating its potential for integration into high-voltage SiC-based power systems. This study provides practical design insights and is expected to contribute to the advancement of wide bandgap semiconductor technologies for next-generation power electronics.

NTC (negative temperature coefficient) thermistors are semiconductor ceramics whose resistance decreases with increasing temperature, making them essential components in various temperature sensing applications. Typically, ceramic materials are sintered at high temperatures exceeding 1,150°C. However, in laminated devices incorporating internal electrodes, co-sintering can lead to cracking and mechanical failure due to mismatches in the thermal expansion coefficients between the ceramic layers and metal-based electrodes. Moreover, the use of noble metal electrodes increases production costs. To address these challenges, a low-temperature sintering approach is required. Previous studies have demonstrated that incorporating glass frit can reduce the sintering temperature of ceramics, although this often results in increased electrical resistance. In this study, NiMnCoO₄ (NMC) ceramics, as a representative NTC thermistor composition, were prepared with the addition of 10 wt% glass frit. To mitigate the resulting increase in resistivity, trace amounts (1 wt%) of various metal oxides, including CuO, ZnO, and MnO, were introduced. Among these, the addition of CuO notably decreased both the resistivity and B constant values. In contrast, MnO had little effect on resistivity, while ZnO led to an increase. With respect to the B25/85 constant, samples containing MnO and ZnO exhibited higher values than those without metal oxide additives. These findings indicate that the incorporation of 1 wt% CuO is effective in reducing the increased resistivity in NMC ceramics subjected to low-temperature sintering via glass frit addition.

Molybdenum disulfide (MoS₂) is a promising 2D semiconductor material for low-power electronics due to its excellent electrical properties and compatibility with conventional processes. In this study, MoS₂ thin films deposited by RF sputtering were etched using Cl₂/Ar plasma in an ICP system. The effects of Cl₂ gas ratio, RF power, and process pressure on etch rate and MoS₂/SiO₂ selectivity were investigated. Optimal results were obtained at 25% Cl₂, achieving ~38 nm/min etch rate and selectivity of 3.0. Increased source power improved both etch rate and selectivity, while higher bias power enhanced etching but reduced selectivity due to stronger ion bombardment. XPS analysis confirmed Mo－Cl and S－Cl bond formation after etching, indicating chemical reactions and some by-product residue. These results provide insights into optimized plasma etching of sputtered MoS₂ films for advanced 2D device fabrication

NTC thermistors are essential components widely used for temperature sensing in various electronic sensor applications. However, conventional NTC thermistor ceramics typically require high sintering temperatures above 1150℃, necessitating the use of high-cost noble metal electrodes such as palladium (Pd) or platinum (Pt), which increases the overall manufacturing cost. In this study, low-melting-point oxides were successfully introduced as sintering aids to reduce the sintering temperature of NiMnCoO₄-based semiconducting ceramics. As the additive content increased, the B constant and average grain size exhibited an increasing trend, while the sample containing 5 wt% additives showed the lowest room-temperature resistivity. Furthermore, samples sintered at 1000℃ demonstrated slightly higher room-temperature resistivity and B constant values compared to those sintered at 1150℃. These results confirm that the addition of low-melting-point oxides is effective in lowering the sintering temperature of NiMnCoO₄ ceramics, suggesting the potential for reducing production costs and improving design flexibility in thermistor fabrication.

With the extensive industrial growth driven by the Fourth Industrial Revolution and the excessive use of fossil fuels, greenhouse gas emissions have accelerated global warming. Energy harvesting technologies have garnered significant attention as a potential solution to this issue. Among them, triboelectric nanogenerators (TENGs) have emerged as promising candidates for energy collection and conversion. However, TENGs typically face limitations in providing an efficient energy supply due to their high output voltage and low output current. To overcome these challenges, numerous studies have explored various methods to enhance the output performance by increasing the surface area of the triboelectric materials. Herein, we report a high-output TENG fabricated through a simple scratch process. By utilizing sandpaper, typically used for abrasion or polishing, the surface roughness of the triboelectric material PFA was increased through surface scratching. The surface-engineered TENG, prepared through this simple and rapid process, demonstrated enhanced output characteristics with a voltage of 276 V and a current of 72 μA, showing a 21% increase in voltage and a 41% increase in current compared to the non-engineered counterpart, providing sufficient energy to power an LED. These results indicate that the scratch-based surface modification process using sandpaper offers an effective solution for improving triboelectric output performance, establishing TENGs as a key contributor to sustainable energy supply.

Next-generation display technologies, including rollable and foldable displays, are advancing rapidly, enabling innovative and versatile form factors. Flexible displays predominantly utilize materials such as Polyimide (PI), Colorless Polyimide (CPI), and Thermoplastic PolyUrethane (TPU) due to their exceptional flexibility and durability. However, a significant challenge lies in the lack of standardized criteria for evaluating the durability of these flexible substrates. In this study, the durability of these materials under rolling conditions was investigated. This study establishes a standardized methodology for evaluating flexible materials used in rollable displays. Experiments were performed on PI, including rolling and scratch tests with varying indenter sizes. Friction data from the scratch tests, combined with cross-sectional analyses, were examined using optical microscopy and Scanning Electron Microscopy (SEM). The scratch test results revealed that PI films with lower elastic recovery exhibited distinct damage patterns during rolling cycles, especially when smaller indenter radius were used. As the number of rolling cycles increased, the critical force decreased rapidly. This behavior was attributed to the weakening or breaking of atomic bonds within the film. This was further confirmed by SEM images, which revealed delamination of the film from the surface after rolling.

This paper presents a Si-NWFET-based LC-VCO design that includes an SCA, a P-type Si-NWFET varactor, a 1.2 nH LC tank, and a bias network to linearize the varactor’s C-V characteristics, enabling a wide oscillation frequency tuning range. The circuit achieves a 24 GHz oscillation frequency with a low power consumption of 16.8 μW at a control voltage (V_ctrl) of 0.7 V. Phase noise simulations indicate an excellent -109.62 dBc/Hz at a 1 MHz offset, confirming its applicability for RFIC systems. Additionally, the proposed LC-VCO demonstrates stable performance in five major corner process analyses, ensuring robustness under extreme conditions. These results validate the durability of the design and highlight the potential of Si-NWFETbased LC-VCOs as a viable, low-power, highly integrated solution for RFIC applications. The findings underscore the suitability of Si-NWFET technology as a promising alternative to current FinFET and CMOS processes in advanced circuit design.

Department of Electric Materials Engineering, Kwangwoon University, Seoul 01897, Korea (Received June 13, 2024; Revised July 8, 2024; Accepted July 10, 2024) Abstract: Wide bandgap (WBG) devices, especially SiC, are gaining traction as materials for high-power EV conversion devices due to their superior efficiency and switching capabilities compared to Si-based power devices. SiC allows for high power, high temperature, and high frequency applications because of its outstanding thermal conductivity, saturation velocity, and dielectric breakdown field. SiC-based MPS diodes combine the advantages of SiC-based SBDs and PiN diodes, allowing high-frequency switching operation with low leakage currents under high voltage conditions. However, MPS diodes exhibit snapback phenomena influenced by the P⁺ region’s size, necessitating optimization. A TCAD simulation studied the impact of the P+ region’s depth and width on MPS diode performance. Increasing the P⁺ width raised the On-specific resistance (R_on,sp) and lowered the maximum voltage during snapback (V_snap). Increasing the depth decreased both Breakdown voltage (BV) and V_snap. A trade-off between the semiconductor performance index BFOM and V_snap was identified, leading to optimized dimensions. The optimized MPS diode shows a low V_snap of about 3.89 V and a high BFOM of 1.72 GW·㎠, highlighting its potential as a next-generation high-performance power conversion device.

Gallium oxide (Ga₂O₃) is emerging as a next-generation power semiconductor material due to its excellent electrical properties, including an ultra-wide bandgap of approximately 4.8 eV and a breakdown electric field of about 7 MV/cm. However, its low thermal conductivity of around 0.13 W/cmK presents significant challenges to the performance and reliability of Ga₂O₃- based devices. In this study, we employed the Silvaco TCAD simulator to analyze the thermal and electrical characteristics of Ga₂O₃ Schottky barrier diodes (SBDs) with heat sinks of varying thermal conductivities. The results demonstrate that heat sinks with higher thermal conductivity effectively mitigate the temperature rise in the device, leading to an increase in current density. The limitation in heat dissipation due to parasitic on-state resistance not only affects device performance but also impacts longterm reliability. Therefore, this study contributes to the development of effective thermal management strategies for Ga₂O₃-based power semiconductors.

This study proposes an innovative methodology for developing flexible printed circuit boards (FPCBs) capable of conforming to three-dimensional shapes, meeting the increasing demand for electronic circuits in diverse and complex product designs. By integrating a traditional flat plate-based fabrication process with a subsequent three-dimensional thermal deformation technique, we have successfully demonstrated an FPCB that maintains stable electrical characteristics despite significant shape deformations. Using a modified polyimide substrate along with Ag flake-based conductive ink, we identified optimized process variables that enable substrate thermal deformation at lower temperatures (~130℃) and enhance the stretchability of the conductive ink (ε ~30%). The application of this novel FPCB in a prototype 3D-shaped sensor device, incorporating photosensors and temperature sensors, illustrates its potential for creating multifunctional, shape-adaptable electronic devices. The sensor can detect external light sources and measure ambient temperature, demonstrating stable operation even after transitioning from a planar to a three-dimensional configuration. This research lays the foundation for next-generation FPCBs that can be seamlessly integrated into various products, ushering in a new era of electronic device design and functionality.

This work focuses on improving the light-harvesting efficiency of thin-film silicon solar cells through innovative multi-architecture surface modifications. To create a regular optical structure, a lithographic process was performed to form it on a glass substrate through various etching processes, from Etch-1 to Etch-3. AZO was deposited on top of the structures and re-etched to create a multi-architectural surface. These surface-modified structures improved the light absorption and overall performance of the solar cell through changes in optical and physical properties, which we will analyze. In addition, we investigated the effect of post-cleaning on the etched glass structures through EDX analysis to understand the mechanism of the etching action. The results of this study are expected to provide important guidelines for the design and fabrication of solar cells and other photovoltaic devices.

High-energy bandgap material silicon carbide (SiC) is gaining attention as a next-generation power semiconductor material, and in particular, SiC-based MOSFETs are developed as representative power semiconductors to increase the breakdown voltage (BV) of conventional planar structures. However, as the size of SJ (Super Junction) MOSFET devices decreases and the depth of pillars increases, it becomes challenging to uniformly form the doping concentration of pillars. Therefore, a structure with different doping concentrations segmented within the pillar is being researched. Using Silvaco TCAD simulation, a SJ VVD (vertical variation doping profile) MOSFET with three different doping concentrations in the pillar was studied. Simulations were conducted for the width of the pillar and the doping concentration of N-epi, revealing that as the width of the pillar increases, the depletion region widens, leading to an increase in on-specific resistance (Ron,sp) and breakdown voltage (BV). Additionally, as the doping concentration of N-epi increases, the number of carriers increases, and the depletion region narrows, resulting in a decrease in Ron,sp and BV. The optimized SJ VVD MOSFET exhibits a very high figure of merit (BFOM) of 13,400 KW/cm², indicating excellent performance characteristics and suggesting its potential as a next-generation highperformance power device suitable for practical applications.

In this study, the structural, electrical, and optical properties of AZO films of various thicknesses are compared. The AZO films were deposited on a glass substrate by FTS (Facing-Target-Sputtering) This research was conducted to find the optimal thickness for Transparent Conductive Oxide (TCO). AZO has suitable properties for TCO such as low resistivity, and high transmittance. Thin films of all thicknesses showed a transmittance of over 80% in the visible light region and electrical properties improved as thickness increased. It was confirmed that the film of 300 nm thick had the best performance due to its low resistivity, and uniform surface. This research is expected to help find optimal conditions in various fields where TCO is used, such as solar cells, displays, and sensors in the future.

(La0.7Sr0.3)(Mn1-xFex)O3 (LSMFO) (x = 0.03, 0.06, 0.09, 0.12) precursor solution are prepared by sol-gel method. LSMFO thin films are fabricated by the spin-coating method on Pt/Ti/SiO2/Si substrate, and the sintering temperature and time are 800℃ and 1 hr, respectively. The average thickness of the 6-times coated LSMFO films is about 181 to 190 nm and average grain size is about 18 to 20 nm. As the amount of Fe added in the LSMFO thin film increased, the resistivity decreased, and the TCR and B25/65-value increased. Electrical resistivity, TCR and B25/65-value of the (La0.7Sr0.3)(Mn0.88Fe0.12)O3 thin film are 0.0136 mΩ-cm, 0.358%/℃, and 328 K at room temperature, respectively. The resistivity properties of LSMFO thin films matched well with Mott’s VRH model.

By introducing curing kinetics and chemo-rheology for the epoxy resin formulation for ultra-high voltage gas insulated switchgear (GIS) Insulating Spacers, a study was conducted to simulate the curing behavior, flow and warpage analysis for optimization of the molding process in automatic pressure gelation. The curing rate equation and chemo-rheology equation were set as fixed values for various factors and other physical property values, and the APG molding process conditions were entered into the Moldflow software to perform optimization numerical simulations of the three-phase insulating spacer. Changes in curing shrinkage according to pack pressure were observed under the optimized process conditions. As a result, it was confirmed that the residence time in the solid state was shortened due to the lowest curing reaction when the curing holding pressure was 3 bar, and the occurrence of deformation due to internal residual stress was minimized.

High-density crossbar arrays based on storage class memory (SCM) are ideally suited to handle an exponential increase in data storage and processing as a central hardware unit in the era of AI-based technologies. To achieve this, selector devices are required to be co-integrated with SCM to address the sneak-path current issue that indispensably arises in such crossbar-type architecture. In this perspective, we first summarize the current state of tellurium-based threshold-switching devices and recent advances in the material, processing, and device aspects. We thoroughly review the physicochemical properties of elemental tellurium (Te) and representative binary tellurides, their tailored deposition techniques, and operating mechanisms when implemented in two-terminal threshold switching devices. Lastly, we discuss the promising research direction of Te-based selectors and possible issues that need to be considered in advance.

Intrinsically stretchable light-emitting diodes, composed of stretchable electrodes, charge transport layers, and luminescent materials, have garnered significant interest for enhancing human well-being and advancing the field of deformable electronics. Various luminescent materials, such as perovskites and organics, have been integrated with stretchable elastomers to function as the stretchable emissive layers in these intrinsically stretchable LEDs. Stretchable conductors including Ag nanowire based percolating structures and conducting polymers have been utilized as stretchable transparent electrode. Despite this progress, their performances in terms of efficiency and stability remain challenging compared to their structurally stretchable and rigid LED counterparts. This review offers a comprehensive overview of recent advancements in intrinsically stretchable LEDs, focusing on material innovations.

Stretchable piezoelectric energy harvester (S-PEHs) based on composite materials are considered one of the potential candidates for realizing wearable self-powered devices for smart clothing and electronic skin. However, low energy conversion performance and expensive stretchable electrodes are major bottlenecks hindering the development and application of S-PEHs. Here, we fabricated the S-PEH by adopting the piezoelectric composites with enhanced stress transfer properties and kirigamipatterned textile electrodes. The optimum contents of piezoelectric BaTiO₃ nanoparticles inside the carbon nanotube/ecoflex composite were selected as 30 wt% considering the trade-off between stretchability and energy harvesting performance of the device. The final S-PEH shows an output voltage and mechanical stability of ~5 V and ~3,000 cycles under repeated 150% of tensile strain, respectively. This work presents a cost-effective and scalable way to fabricate stretchable piezoelectric devices for self-powered wearable electronic systems.

Flexible fiber- or yarn-based one-dimensional (1-D) energy storage devices are essential for developing wearable electronics and have thus attracted considerable attention in various fields including ubiquitous healthcare (U-healthcare) systems and textile platforms. 1-D supercapacitors (SCs), in particular, are recognized as one of the most promising candidates to power wearable electronics due to their unique energy storage and high adaptability for the human body. They can be woven into textiles or effectively designed into diverse architectures for practical use in day-to-day life. This review summarizes recent important development and advances in fiber-based supercapacitors, concerning the active materials, fiber configuration, and applications. Active materials intended to enhance energy storage capability including carbon nanomaterials, metal oxides, and conductive polymers, are first discussed. With their loading methods for fiber electrodes, a summary of the four main types of fiber SCs (e.g., coil, supercoil, buckle, and hybrid structures) is then provided, followed by demonstrations of some practical applications including wearability and power supplies. Finally, the current challenges and perspectives in this field are made for future works.

La_0.7-xCe_xSr_0.3MnO₃ specimens were fabricated by a solid state reaction method and structural and electrical properties with variation of Ce4+ contents were measured. All specimens exhibited a polycrystalline rhombohedral crystal structure, and the (110) peaks were shifted to low angle side with increasing the amount of Ce⁴⁺ contents. As Ce⁴⁺ ions with different ion radii and charges are substituted with La³⁺ ions, electrical properties are thought to be affected by changes in the double exchange interaction between Mn³⁺-Mn⁴⁺ ions due to distortion of the unit lattice, a decrease in oxygen vacancy concentration, and an increase in lattice defects. Resistivity gradually decrease as the amount of Ce⁴⁺ added increased, and negative temperature coefficient of resistance (NTCR) properties were shown in all specimens. In the La_0.5Ce_0.2Sr_0.3MnO₃ specimens, electrical resistivity, TCR and B-value were 31.8 Ω-cm, 0.55%/℃ and 605 K, respectively.

Integrating dielectric materials into LTCC is a convenient method to increase the integration density in electronic circuits. To enable co-firing of the high-k and low-k dielectric LTCC materials in a multi-material hetero-laminate, the shrinkage characteristics of both materials should be similar. Moreover, thermal expansion mismatch between materials during co-firing should be minimized. The alternating stacking of an LTCC with silica filler and that with calcium-zirconate filler was observed to examine the use of the same glass in different LTCCs to minimize the difference in shrinkage and thermal expansion coefficient. For the LTCC of silica filler with a low dielectric constant and that of calcium zirconate filler with a high dielectric constant, the amount of shrinkage was examined through a thermomechanical analysis, and the predicted appropriate fraction of each filler was applied to green sheets by tape casting. The green sheets of different fillers were alternatingly laminated to the thickness of 500 ㎛. As a result of examining the junction, it was observed through SEM that a complete bonding was achieved by constrained sintering in the structure of ‘calcium zirconate 50 vol%-silica 30 vol%-calcium zirconate 50 vol%’.

For decades, sputtering as a physical vapor deposition (PVD) method has been a widely used technique for film coating processes. The sputtering enables oxides, metals, alloys, nitrides, etc to be deposited on a wide variety of substrates from silicon wafers to polymer substrates. Meanwhile, transparent conductive oxides (TCOs) have played important roles as electrodes in electrical applications such as displays, sensors, solar cells, and thin-film transistors. TCO films fabricated through a sputtering process have a higher quality leading to an improved device performance than other films prepared with other methods. In this review, we discuss the mechanism of sputtering deposition and detail the TCO materials. Related technologies (processing conditions, materials, and applications) are introduced for electrical applications.

Currently, semiconductor manufacturing industry heavily relies on a wide range of high global warming potential (GWP) gases, particularly during etching and cleaning processes, and their use and relevant carbon emissions are subject to global rules and regulations for achieving carbon neutrality by 2050. To replace high GWP gases in near future, dry etching using alternative low GWP gases is thus being under intense investigations. In this review, we report a current status and recent progress of the relevant research activities on dry etching processes using a low GWP gas. First, we review the concept of GWP itself and then introduce the difference between high and low GWP gases. Although most of the studies have concentrated on potentially replaceable additive gases such as C₄F₈, an ultimate solution with a lower GWP for main etching gases including CF₄ should be developed; therefore, we provide our own perspective in this regard. Finally, we summarize the advanced dry etch process research with low GWP gases and list up several issues to be considered in future research.

Ultrasonic sensor is suitable as a next-generation autonomous driving assist device because its lower price compared to that of other sensors and its sensing stability in the external environment. Although Pb(Zr, Ti)O₃ (PZT)-relaxor ferroelectric system has excellent piezoelectric properties, the change in capacitance is large in the daily operating temperature range due to the low phase transition temperature. Recently, many studies have been conducted to improve the temperature stability of ferroelectric ceramics by controlling the grain size and crystal structure, so it is necessary to study the effect of the grain size on the piezoelectric properties and the temperature stability of PZT-relaxor ferroelectric system. In this study, the piezoelectric properties, phase transition temperature, and temperature coefficient of capacitance (TCC) of 0.9 Pb(Zr_1-xTi_x)O₃-0.1 Pb(Zn_1/3Nb_2/3)O₃ (PZT_x-PZN) ceramics with various grain sizes were investigated. PZT_x-PZN ceramics with larger grain size showed higher piezoelectric properties and temperature stability, and are expected to be suitable for ultrasonic devices in the future.

Single crystal gallium oxide (Ga₂O₃) has been an emerging material for power semiconductor applications. However, the defect distribution of Ga₂O₃ substrates needs to be carefully characterized to improve crystal quality during crystal growth. We analyzed the type and the distribution of defects on commercial (-201) Ga₂O₃ substrates to get a basic standard prior to growing Ga₂O₃ crystals. Etch pit technique was employed to expose the type of defects on the Ga₂O₃ substrates. Synchrotron white beam X-ray topography was also utilized to observe the defect distribution by a nondestructive manner. We expect that the observation of defect distribution with three-dimensional geometry will also be useful for other crystal planes of Ga₂O₃ single crystals.

Bulky iron-core potential transformers (PT) are installed in a tank of gas insulated switchgears (GIS) for a system voltage measurement in power substations. In this paper, we studied an electronic voltage transformer (EVT) embedded in a spacer for miniaturization, eco-friendliness, and performance improvement of GIS. The prototype EVT consists of a capacitive probe (CP) that can be embedded in a spacer and a voltage Follower with a high input and a low output impedance. The CP was fabricated in the form of a Flexible-PCB to acquire the insulation performance and to withstand vibration and shock during operation. Voltage ratio of the prototype EVT is about 42,270, and the frequency bandwidth of -3 dB ranges from 0.33 Hz to 3.9 MHz. The voltage ratio error evaluated at about 6%, 12% and 18% of the rated voltage of 170 kV was 0.32%, and the phase error was 12.9 minutes. These results were within the accuracy for the class 0.5 specified in IEC 60044-7 and satisfy even in ranges from 80% to 120% of the rated voltage. If the prototype EVT replaces the conventional iron-core potential transformer, it is expected that the height of the GIS could be reduced by 11% and the amount of SF6 will be reduced by at least 10%.

Resistive switching behaviors of a co-sputtered zinc silicate thin film (ZnO and SiO₂ targets) have been investigated. We fabricated an Ag/ZnSiO_x/highly doped n-type Si substrate device by using an RF magnetron sputter system. X-ray diffraction pattern (XRD) indicated that the Zn₂SiO₄ was formed by a post annealing process. A unique morphology was observed by scanning electron microscope (SEM) and atomic force microscope (AFM). As a result of annealing process, 50 nm sized nano clusters were formed spontaneously in 200~300 nm sized grains. The device showed a unipolar resistive switching process. The average value of the ratio of the resistance change between the high resistance state (HRS) and the low resistance state (LRS) was about 106 when the readout voltage (0.5 V) was achieved. Resistance ratio is not degraded during 50 switching cycles. The conduction mechanisms were explained by using Ohmic conduction for the LRS and Schottky emission for the HRS.