In electrical power substations, bulky iron-core potential transformers (PTs) are installed in a tank of gas-insulated switchgear (GIS) to measure system voltages. This paper proposed a low-power voltage transformer (LPVT) that can replace the conventional iron-core PTs in response to the demand for the digitalization of substations. The prototype LPVT consists of a capacitive voltage divider (CVD) which is embedded in a spacer and an impedance matching circuit using passive components. The CVD was fabricated with a flexible PCB to acquire enough insulation performance and withstand vibration and shock during operation. The performance of the LPVT was evaluated at 80%, 100%, and 120% of the rated voltage (38.1 kV) according to IEC 61869-11. An accuracy correction algorithm based on LabVIEW was applied to correct the voltage ratio and phase error. The corrected voltage ratio and phase error were +0.134% and +0.079 min., respectively, which satisfies the accuracy CL 0.2. In addition, the voltage ratio of LPVT was analyzed in ranges of -40~+40℃, and a temperature correction coefficient was applied to maintain the accuracy CL 0.2. By applying the LPVT proposed in this paper to the same rating GIS, it can be reduced the length per GIS bay by 11%, and the amount of SF6 by 5~7%.

Bulky iron-core potential transformers (PT) are installed in a tank of gas insulated switchgears (GIS) for a system voltage measurement in power substations. In this paper, we studied an electronic voltage transformer (EVT) embedded in a spacer for miniaturization, eco-friendliness, and performance improvement of GIS. The prototype EVT consists of a capacitive probe (CP) that can be embedded in a spacer and a voltage Follower with a high input and a low output impedance. The CP was fabricated in the form of a Flexible-PCB to acquire the insulation performance and to withstand vibration and shock during operation. Voltage ratio of the prototype EVT is about 42,270, and the frequency bandwidth of -3 dB ranges from 0.33 Hz to 3.9 MHz. The voltage ratio error evaluated at about 6%, 12% and 18% of the rated voltage of 170 kV was 0.32%, and the phase error was 12.9 minutes. These results were within the accuracy for the class 0.5 specified in IEC 60044-7 and satisfy even in ranges from 80% to 120% of the rated voltage. If the prototype EVT replaces the conventional iron-core potential transformer, it is expected that the height of the GIS could be reduced by 11% and the amount of SF6 will be reduced by at least 10%.

Although there is no strict definition of a power semiconductor device, a general description is a semiconductor that has capability to control more than 1 W of electricity. Integrated gate bipolar transistors (IGBTs), which are power semiconductors, are widely used in voltage ranges above 300 V and are especially popular in high-efficiency, high-speed power systems. In this paper, the size of the gate was adjusted to test the variation in the yield voltage characteristics by measuring the electric field concentration under the trench gate. After the experiment Synopsys’ TCAD was used to analyze the efficiency of threshold voltage, on-state voltage drop, and breakdown voltage by measuring the P- region and its size under the gate.

Among several types of energy saving smart window technologies, the leader, the dynamic EC (electrochromic) window one needs integrated PV (photovoltaics), to minimize expensive electrical wiring as well as to obviate the need for external energy. Self-powered smart windows were reviewed according to PV types used. DSSCs (dye sensitized solar cells) were found to be compatible with EC cells, to have several categories of next generation smart windows such as PECCs (photoelectrochromic cells), PVCCs (photovoltachromic cells), EC polymer PECCs. In addition silicon solar cells and third generation solar cells were investigated. They are summarized in a table showing their advantages and disadvantages respectively for a fast comparison. The strategy to expedite the commercialization of these next generation smart windows includes developing retrofit smart window coverings for use on flexible polymer substrates adhered to the inside surface of a window and easily replaced after use for upto 10 years.

SiC crystal ingots were grown on 6H-SiC dual-seed crystals with different surface roughness and different seed orientation by a PVT (Physical Vapor Transport) method. 4H and 15R-SiC were grown on seed crystal with high root-mean-square (rms) value. The polytype of grown crystal on the seed crystal with lower rms value was confirmed to be 6H-SiC. On the other hand, all SiC crystals grown on seed crystals with different seed orientation were proven to be 6H-SiC. The surface roughness of seed crystals had no effect on the crystal structure of the grown crystals. However, the crystal quality of 6H-SiC single crystals grown on the on-axis seed were revealed to be slightly better than that of 6H-SiC crystal grown on the off-axis seed.

The self-cascode (SC) structure has low output voltage swing and high output resistance. In order to implement a simple and better SC structure, the native-Vth MOSFETs which has low threshold voltage (Vth) is applied. The proposed SC structure is designed using a qualified industry standard 0.18-㎛ CMOS technology. Measurement results show that the proposed SC structure has higher transconductance as well as output resistance than single MOSFET. In addition, analog building blocks (e.g. current mirror, basic amplifier circuits) with the proposed SC structure are investigated using by Cadence Spectre simulator. Simulation results show improved electrical performances.

Power Metal Oxide Semiconductor Field Effect Transistor`s (MOSFETs) are well known for superior switching speed, and they require very little gate drive power because of the insulated gate. In these respects, power MOSFETs approach the characteristics of an “ideal switch”. The main drawback is on-resistance RDS(on) and its strong positive temperature coefficient. While this process has been driven by market place competition with operating parameters determined by products, manufacturing technology innovations that have not necessarily followed such a consistent path have enabled it. This treatise briefly examines metal oxide semiconductor (MOS) device characteristics and elucidates important future issues which semiconductor technologists face as they attempt to continue the rate of progress to the identified terminus of the technology shrink path in about 2020. We could find at the electrical property as variation p base dose. Ultimately, its ON state voltage drop was enhanced also shrink chip size. To obtain an optimized parameter and design, we have simulated over 500 V Field ring using 8 Field rings. Field ring width was 3 ㎛ and P base dose was 1e15 ㎠. Also the numerical multiple 2.52 ㎠ was obtained which indicates the doping limit of the original device. We have simulated diffusion condition was split from 1,150℃ to 1,200℃. And then 1,150℃ diffusion time was best condition for break down voltage.

Power MOSFETs(Metal Oxide Semiconductor Field Effect Transistor) operate as energy control semiconductor switches. In order to reduce energy loss of the device during switch-on state, it is essential to increase its conductance. We have experimental results and explanations on the doping profile dependence of the electrical behavior of the vertical MOSFET. The device is fabricated as 8.25 ㎛ cell pitch and 4.25 ㎛ gate width. The performances of device with various p base doping concentration are compared at Vth from 1.77 V to 4.13 V. Also the effect of the cell structure on the on-resistance and breakdown voltage of the device are analyzed. The simulation results suggest that the device optimized for various applications can be further optimized at power device.

In this study, SiC single-crystal ingots were prepared on two seed crystals with different doping level by using the physical vapor transport (PVT) technique; then, SiC crystal wafers sliced from the grown SiC ingot were systematically investigated to find the effect of seed doping level on the doping concentration and crystal quality of the SiC. To exclude extra effects induced by adjustment of the process parameters, we simultaneously grew the SiC crystals on two seed crystals with different level, which were fabricated from previous two SiC crystal ingots.