Skip to main navigation Skip to main content
  • KIEEME

J Electr Electron Mater : Journal of Electrical and Electronic Materials

OPEN ACCESS
Search
Advanced Search
ABOUT
BROWSE ARTICLES
EDITORIAL POLICIES
FOR CONTRIBUTORS

Articles

Page Path

비휘발성 메모리를 위한 SiO2와 Si3N4가 대칭적으로 적층된 터널링 절연막의 전기적 특성과 열처리를 통한 특성 개선효과

김민수, 정명호, 김관수, 박군호, 정종완, 정홍배, 이영희, 조원주

Improved Electrical Characteristics of Symmetrical Tunneling Dielectrics Stacked with SiO2 and Si3N4 Layers by Annealing Processes for Non-volatile Memory Applications

Min Soo Kim, Myung Ho Jung, Kwan Su Kim, Goon Ho Park, Jong Wan Jung, Hong Bay Chung, Young Hie Lee, Won Ju Cho
J Electr Electron Mater 2009;22(5):386-389.
Published online: May 1, 2009
  • 10 Views
  • 0 Download
  • 0 Crossref
  • 0 Scopus
prev next

Full Article

Download PDF Download PDF

Download Citation

Download a citation file in RIS format that can be imported by all major citation management software, including EndNote, ProCite, RefWorks, and Reference Manager.

Format:

Include:

Improved Electrical Characteristics of Symmetrical Tunneling Dielectrics Stacked with SiO2 and Si3N4 Layers by Annealing Processes for Non-volatile Memory Applications
J Electr Electron Mater. 2009;22(5):386-389.   Published online May 1, 2009
Download Citation

Download a citation file in RIS format that can be imported by all major citation management software, including EndNote, ProCite, RefWorks, and Reference Manager.
Format:
Include:
Improved Electrical Characteristics of Symmetrical Tunneling Dielectrics Stacked with SiO2 and Si3N4 Layers by Annealing Processes for Non-volatile Memory Applications
J Electr Electron Mater. 2009;22(5):386-389.   Published online May 1, 2009
Close

Related articles

ABOUT

BROWSE ARTICLES

EDITORIAL POLICIES

FOR CONTRIBUTORS

© The Korean Institute of Electrical and Electronic Materials Engineers.