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J Electr Electron Mater : Journal of Electrical and Electronic Materials

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SABiT 공법적용 인쇄회로기판의 은 페이스트 범프 크기 및 제작 조건에 따른 전기 저항 특성

송철호, 김영훈, 이상민, 목지수, 양용석

Characterization of Electrical Resistance for SABiT Technology-Applied PCB: Dependence of Bump Size and Fabrication Condition

Chul Ho Song, Young Hun Kim, Sang Min Lee, Jee Soo Mok, Yong Suk Yang
J Electr Electron Mater 2010;23(4):298-302.
Published online: April 1, 2010
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Characterization of Electrical Resistance for SABiT Technology-Applied PCB: Dependence of Bump Size and Fabrication Condition
J Electr Electron Mater. 2010;23(4):298-302.   Published online April 1, 2010
Download Citation

Download a citation file in RIS format that can be imported by all major citation management software, including EndNote, ProCite, RefWorks, and Reference Manager.

Format:
Include:
Characterization of Electrical Resistance for SABiT Technology-Applied PCB: Dependence of Bump Size and Fabrication Condition
J Electr Electron Mater. 2010;23(4):298-302.   Published online April 1, 2010
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