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TSV 웨이퍼 공정용 Si3N4 후막 스트레스에 대한 공정특성 분석

강동현, 구종모, 고영돈, 홍상진

Characterization of Backside Passivation Process for Through Silicon via Wafer

Dong Hyun Kang, Jung Mo Gu, Young Don Ko, Sang Jeen Hong
J Electr Electron Mater 2014;27(3):137-140.
Published online: March 1, 2014
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Through silicon vias (TSV) 공정기술의 발전으로 TSV 웨이퍼 양산적용이 가능하게 됨에 따라, 생산력 향상을 위한 TSV 웨이퍼용 고속 후막증착과 낮은 박막응력을 갖는 증착 장비의 개발이 시급하게 되었다. 본 연구는 300 mm 웨이퍼를 사용하는 PECVD 장비를 사용하여 진행하였다. 공정 모델링을 위하여 15개의 300 mm 웨이퍼 위에 Si3N4박막을 증착하고 박막의 Stress를 측정하였으며, 공정조건과 박막의 스트레스 간의 관계를 통계적으로 분석하여, 공정변수와 반응변수 간의 물리적 관계를 파악하고, 모델링을 통해 공정결과를 분석하였다.

With the recent advent of through silicon via (TSV) technology, wafer level-TSV interconnection become feasible in high volume manufacturing. To increase the manufacturing productivity, it is required to develop equipment for backside passivation layer deposition for TSV wafer bonding process with high deposition rate and low film stress. In this research, we investigated the relationship between process parameters and the induced wafer stress of PECVD silicon nitride film on 300mm wafers employing statistical and artificial intelligence modeling. We found that the film stress increases with increased RF power, but the pressure has inversely proportional to the stress. It is also observed that no significant stress change is observed when the gas flow rate is low.

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Characterization of Backside Passivation Process for Through Silicon via Wafer
J Electr Electron Mater. 2014;27(3):137-140.   Published online March 1, 2014
Download Citation

Download a citation file in RIS format that can be imported by all major citation management software, including EndNote, ProCite, RefWorks, and Reference Manager.

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Characterization of Backside Passivation Process for Through Silicon via Wafer
J Electr Electron Mater. 2014;27(3):137-140.   Published online March 1, 2014
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