4H-SiC power metal-oxide-semiconductor field effect transistors (MOSFETs) have been developed to achieve lower specific-on-resistance (Ron,sp), and the gate oxides have been thermally grown. The poor channel mobility resulting from the high interface trap density (Dit) at the SiO2/4H-SiC interface significantly affects the higher switching loss of the power device. Therefore, the development of novel fabrication processes to enhance the quality of the SiO2/4H-SiC interface is required. In this paper, NO post-oxidation annealing (POA) by using the conditions of N2 diluted NO at a high temperature (1,300℃) is proposed to reduce the high interface trap density resulting from thermal oxidation. The NO POA is carried out in various NO ambient (0, 10, 50, and 100% NO mixed with 100, 90, 50, and 0% of high purity N2 gas to achieve the optimized condition while maintaining a high temperature (1,300℃). To confirm the optimized condition of the NO POA, measuring capacitance-voltage (C-V) and current-voltage (I-V), and time-of-flight secondary-ion mass spectrometry (ToF-SIMS) are employed. It is confirmed that the POA condition of 50% NO at 1,300℃ facilitates the equilibrium state of both the oxidation and nitridation at the SiO2/4H-SiC interface, thereby reducing the Dit.
