Drain Induced Barrier Lowering (DIBL) was analyzed when the channel of Gate-All-Around (GAA) FET, which is the most promising in the miniaturizing transistor structure, has an elliptic cross-section. The oxide film structure used a stacked Metal-Ferroelectric-Metal-Insulator-Semiconductor (MFMIS) structure using SiO2 and ferroelectric. An analytical DIBL model was presented to analyze the DIBL in elliptic GAA FET with ferroelectric. Its validity was proven by comparing the results of other papers. As a result, the Drain Induced Barrier Rising (DIBR) effect, that is, the negative DIBL effect, appeared depending on the ferroelectric thickness tfe, and the ratio of the remanent polarization Pr and coercive field Ec in the ferroelectric, Pr/Ec. The DIBL varied linearly with tfeEc/Pr, and the slope depended on the rate of change for the drain voltage of the ferroelectric charge Q, dQ/dVds. The tfeEc/Pr value satisfying DIBL=0 mV/V decreased as eccentricity increased. The ferroelectric thickness tfe will have to be decreased because the subthreshold swing increases if the Pr/Ec is increased to reduce the tfeEc/Pr value. The threshold voltage increased at this time, but the effect was minimal.
