In this paper, we report that selective etching on N-polar face by EC (electro-chemical)-etching effect on the reduction of bowing and strain of FS (free-standing)-GaN substrates. We applied the EC-etching to concave and convex type of FS-GaN substrates. After the EC-etching for FS-GaN, nano porous structure was formed on N-polar face of concave and convex type of FS-GaN. Consequently, the bowing in the convex type of FS-GaN substrate was decreased but the bowing in the concave type of FS-GaN substrate was increased. Furthermore, the FWHM (full width at half maximum) of (1 0 2) reflection for the convex type of FS-GaN was significantly decreased from 601 to 259 arcsec. In the case, we confirmed that the EC-etching method was very effective to reduce the bowing in the convex type of FS-GaN and the compressive stress in N-polar face of convex type of FS-GaN was fully released by Raman measurement.

We investigated and compared two methods of in-situ oxidation and chemical etching treatment (CET) to remove the boron rich layer (BRL). The BRL is generally formed during boron doping process. It has to be controlled in order not to degrade carrier lifetime and reduce electrical properties. A boron emitter is formed using BBr3 liquid source at 930℃. After that, in-situ oxidation was followed by injecting oxygen of 1,000 sccm into the furnace during ramp down step and compared with CET using a mixture of acid solution for a short time. Then, we analyzed passivation effect by depositing Al2O3. The results gave a carrier lifetime of 110.9 ㎲, an open-circuit voltage (Voc) of 635 mV at in-situ oxidation and a carrier lifetime of 188.5 ㎲, an Voc of 650 mV at CET. As a result, CET shows better properties than in-situ oxidation because of removing BRL uniformly.

For integrated complementary metal oxide semiconductor (CMOS) circuits, the lateral spread for two-dimensional (2-D) impurity distributions are very important for the analyzing the devices. The measured two-dimensional SEM data obtained using the chemical etching-method matched very well with the results of the Gauss model for boron implanted samples. But the profiles in boron implanted silicon were deviated from the Gauss model. The profiles in boron implanted silicon were shown a little bit steep profile in the deep region due to backscattering effect on the near surface from the bombardments of light boron ions. From the simulated 3-D data obtained using an analytical model, the 1-D and 2-D data were compared with the experimental data and could be verified the justification from the experimental data. The data of 3-D model were also shown good agreements with the experimental and the simulated data. It can be used in the 3-D chip design and the analysis of microelectro-mecanical system (MEMS) and special devices.

Even though nano-scale materials were very advantageous for various applications, there are still problems to be solved such as the stabilization of surface state and realization of low contact resistances between a semiconducting nanowire and electrodes in nano-electronics. It is well known that the effects of contacts barrier between nano-channel and metal electrodes were dominant in carrier transportation in individual nano-electronics. In this report, it was investigated the electrical properties of GaN nanorod devices after chemical etching and rapid thermal annealing for making good contacts. After KOH wet-etching of the contact area the devices showed better electrical performance compared with non-treated GaN individual devices but still didn`t have linear voltage-current characteristics. The shape of voltage-current properties of GaN devices were improved remarkably after rapid thermal annealing as showing Ohmic behaviors with further bigger conductivities. Even though chemical etching of the nanorod surfaces could cause scattering of carriers, in here it was shown that the most important and dominant factor in carrier transport of nano-electronics was realization of low contact barrier between nano-channel and metal electrodes surely.