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J Electr Electron Mater : Journal of Electrical and Electronic Materials

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고용량 적층 세라믹 커패시터에서 설계 및 제조공정에 따른 전기적 특성 평가

윤중락, 우병철, 이헌용, 이석원

Design and Fabrication Process Effects on Electrical Properties in High Capacitance Multilayer Ceramic Capacitor

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J Electr Electron Mater 2007;20(2):118-123.
Published online: February 1, 2007
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Design and Fabrication Process Effects on Electrical Properties in High Capacitance Multilayer Ceramic Capacitor
J Electr Electron Mater. 2007;20(2):118-123.   Published online February 1, 2007
Download Citation

Download a citation file in RIS format that can be imported by all major citation management software, including EndNote, ProCite, RefWorks, and Reference Manager.

Format:
Include:
Design and Fabrication Process Effects on Electrical Properties in High Capacitance Multilayer Ceramic Capacitor
J Electr Electron Mater. 2007;20(2):118-123.   Published online February 1, 2007
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