Ion-beam sputtering (IBS) was used to deposit semiconducting IZTO (indium zinc tin oxide) thin films onto heavily-doped Si substrates using a sintered ceramic target with the nominal composition In_0.4Zn_0.5Sn_0.1O_1.5, which could work as a channel layer for oxide TFT (oxide thin film transistor) devices. The crystallization behavior and electrical properties were examined for the films in terms of deposition parameters, i.e. target tilt angle and substrate temperature during deposition. The thickness uniformity of the films were examined using a stylus profilometer. The observed difference in electrical properties was not related to the degree of crystallization but to the deposition temperature which affected charge carrier concentration (n), electrical resistivity (ρ), sheet resistance (R_s), and Hall mobility (μH) values of the films.

Oxide semiconductor devices have become increasingly important because of their high mobility and good uniformity. The channel length of oxide semiconductor thin film transistors (TFTs) also shrinks as the display resolution increases. It is well known that reducing the channel length of a TFT is detrimental to the current saturation because of drain-induced barrier lowering, as well as the movement of the pinch-off point. In an organic light-emitting diode (OLED), the lack of current saturation in the driving TFT creates a major problem in the control of OLED current. To obtain improved current saturation in short channels, we fabricated indium gallium zinc oxide (IGZO) TFTs with single gate and double gate structures, and evaluated the electrical characteristics of both devices. For the double gate structure, we connected the bottom gate electrode to the source electrode, so that the electric potential of the bottom gate was fixed to that of the source. We denote the double gate structure with the bottom gate fixed at the source potential as the BGFP (bottom gate with fixed potential) structure. For the BGFP TFT, the current saturation, as determined by the output characteristics, is better than that of the conventional single gate TFT. This is because the change in the source side potential barrier by the drain field has been suppressed.

Thin film transistors (TFTs) with large-area, high mobility, and high reliability are important factors for next-generation displays. In particular, thin transistors based on IGZO oxide semiconductors are being actively researched for this application. In this study, several methods for improving the reliability of a-IGZO TFTs by applying various materials on a passivation layer are investigated. In the literature, inorganic SiO₂, TiO₂, Al₂O₃, ZTSO, and organic CYTOP have been used for passivation. In the case of Al₂O₃, excellent stability is exhibited compared to the non-passivation TFT under the conditions of negative bias illumination stress (NBIS) for 3 wavelengths (R, G, B). When CYTOP passivation, SiO₂ passivation, and non-passivation devices were compared under the same positive bias temperature stress (PBTS), the Vth shifts were 2.8 V, 3.3 V, and 4.5 V, respectively. The Vth shifts of TiO₂ passivation and non-passivation devices under the same NBTS were -2.2 V and -3.8 V, respectively. It is expected that the presented results will form the basis for further research to improve the reliability of a-IGZO TFT.

We investigated solution-processed indium-zinc oxide (IZO) thin-film transistors (TFTs) by inserting a 2-(4- biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole (PBD) buffer layer. This buffer layer efficiently tuned the energy level between the semiconducting oxide channel and metal electrode by increasing charge extraction, thereby enhancing the overall device performance: the IZO TFT with embedded PBD layer (thickness: 5 nm; width: 2,000 μm; length: 200 μm) exhibited a field-effect mobility of 1.31 cm²V^-1s^-1, threshold voltage of 0.12 V, subthreshold swing of 0.87 V decade^-1, and on/off current ratio of 9.28×10⁵.

We report on amorphous thin-film transistors (TFTs) with indium zinc oxide (IZO) channel layers that were fabricated via a solution process. We prepared the IZO semiconductor solution with 0.1 M indium nitrate hydrate and 0.1 M zinc acetate dehydrate as precursor solutions. The solution- processed IZO TFTs showed good performance: a field-effect mobility of 7.29 ㎠/Vs, a threshold voltage of 4.66 V, a subthreshold slope of 0.48 V/dec, and a current on-to-off ratio of 1.62×10⁵. To investigate the static response of our solution-processed IZO TFTs, simple resistor load-type inverters were fabricated by connecting a 2-MΩ resistor. Our IZOTFTbased N-MOS inverter performed well at operating voltage, and therefore, isa good candidate for advanced logic circuits and display backplane.

The ultimate aims of display market is transparent or flexible. Researches have been carried out for various applications. It has been possible to reduced the process steps and get good electrical properties for semiconductors with large optical bandgaps. Oxide semiconductors have been established as one of the leading and promising technology for next generation display panels. In this paper, alternative treatment processes have been tried for oxide semiconductors of thin film transistors to increase the electrical properties of the thin film transistors and to investigate the mechanisms. There exist a various oxide semiconductors. Here, we focused on InGaZnO, ZnO and InSnZnO which are commercialized or researched actively.

We have investigated the effect of electrical properties of amorphous InGaZnO thin filmtransistors (a-IGZO TFTs) by post thermal annealing in O2 ambient.The post-annealed in O2 ambienta-IGZOTFT is found to be more stable to be used for oxide-based TFT devices, and has betterperformance, such as the on/off current ratios, sub-threshold voltage gate swing, and, as well asreasonable threshold voltage, than others do. The interface trap density is controlled to achieve theoptimum value of TFT transfer and output characteristics. The device performance is significantlyaffected by adjusting the annealing condition. This effect is closely related with the modulation annealingmethod by reducing the localized trapping carriers and defect centers at the interface or in the channellayer.