There is an increasing demand for freeform stretchable display technologies capable of overcoming spatial limitations in next-generation platforms such as augmented reality (AR) and virtual reality (VR). To realize such stretchable displays, all constituent materials—including semiconductors, electrodes, insulators, and substrates—must exhibit sufficient mechanical elasticity. To date, stretchable gate insulators have primarily relied on organic polymers such as poly(4-vinylphenol-co-methyl methacrylate) (PVP-co-PMMA). However, their practical application is significantly limited by poor electrical properties, including low dielectric constant and instability. In this work, we propose a novel gate insulator structure that minimizes the use of solution-based processes, which often suffer from poor uniformity and may damage underlying layers during fabrication. The proposed structure integrates the advantages of both organic and inorganic materials by employing a hybrid configuration. Specifically, high-k HfO₂ thin films are deposited on both the top and bottom of an organic layer composed of PVP-co-PMMA, poly(melamine-co-formaldehyde) (PMF) as a crosslinking agent, and propylene glycol monomethyl ether acetate (PGMEA) as a solvent. This inorganic–organic–inorganic structure effectively compensates for the inherent electrical limitations of organic materials. As a result, the fabricated thin-film transistors (TFTs) exhibit improved electrical performance and reliability compared to devices employing a single organic gate insulator.

Neuromorphic computing, which mimics the energy-efficient parallel processing capabilities of the human brain, has emerged as an alternative to traditional von Neumann architectures that struggle with high power consumption in the era of artificial intelligence (AI). Despite the potential of Si-based neuromorphic chips, they often face fundamental limitations in integration density and biological compatibility, necessitating the development of next-generation devices that can better emulate the ionic signaling of biological systems. This review provides a comprehensive analysis of the recent research trends in artificial synapses and neurons based on organic electrochemical transistors (OECTs), highlighting their unique ability to achieve high transconductance and mixed ionic-electronic conduction at ultra-low operating voltages. We discuss how OECTs successfully replicate diverse synaptic plasticities and complex neuronal spiking behaviors through advanced material engineering and structural optimizations such as vertical architectures. Furthermore, this review discusses the implementation of high-order neural functions, including associative learning and logic operations, which are facilitated by the inherent electrochemical dynamics of organic semiconductors. Finally, overcoming current challenges in reliability and scalability will establish OECTs as a pivotal platform for low-power neuromorphic hardware and bio-integrated electronics.

With the advancement of the information society, the demand for highly integrated and multi-functional electronic devices is rapidly increasing. To meet these demands, high-performance transistors with low power consumption, high-speed operating, and mechanical flexibility are essential. Among various candidates, semiconducting single-walled carbon nanotubes (s-SWCNT)-based transistors, which exhibit intrinsically ambipolar characteristics, have emerged as promising components for CMOS-like circuits. In this study, s-SWCNT were selectively dispersed using rr-P3DDT, a thiophene-based conjugated polymer, and filed-effect transistors (FETs) were fabricated by inducting directional alignment for enhanced charge transport through an off-centered spin-coating process. The electrical characteristics of the fabricated s-SWCNT FETs were evaluated under various thermal annealing conditions (100℃, 150℃, 200℃, and 250℃). Off-centered spin-coated and high temperature annealed s- SWCNT FETs exhibited high field-effect mobilities over 5 cm²/Vs in both p-type and n-type operation, along with ideal Vshaped ambipolar transfer curves. These results indicate a significant enhancement in ambipolar performance due to efficient desorption of residual oxygen and water molecules in active channel via high temperature annealing. Furthermore, CMOS-like inverter circuits demonstrated an ideal inversion voltage (VIN = V_DD/2) and a high voltage gain of approximately 9.5. These findings highlight the potential of SWCNT-based materials for realizing next-generation flexible electronic circuits that combine high-performance, energy efficiency, and simplified solution-processing.

In this study, we investigated the electrical stability and performance enhancement of In₂O₃ thin-film transistors (TFTs) through hydrogen peroxide (H₂O₂) and ultraviolet (UV) treatment under controlled temperature conditions. The In₂O₃ TFTs were fabricated using a sol-gel process, followed by H₂O₂ treatment at 40, 50, and 60℃ in combination with UV irradiation. The impact of these processing conditions on the device characteristics, including mobility (μ), threshold voltage (Vth), subthreshold swing (S/S), and on/off current ratio, was systematically analyzed. The results indicate that the 50℃ TFTs exhibited the most stable electrical performance, with minimal Vth shift under negative bias stress (NBS) conditions and optimized switching behavior. Furthermore, static inverter measurements confirmed the reliable voltage transfer characteristics (VTCs) and gain performance of the optimized In₂O₃ TFTs. These findings suggest that the proposed H₂O₂ and UV treatment technique can effectively improve the reliability and long-term stability of In₂O₃-based electronic devices, making them promising candidates for future electronic applications.

Recently, oxide semiconductors have assumed a pivotal role in electronic displays and transparent electronic devices such as amorphous indium gallium zinc oxide (a-IGZO), characterized by high electron mobility and excellent stability. a- IGZO is very suitable for next-generation applications such as flexible displays because it is possible to manufacture highperformance transistors even at low temperatures. However, since the electrical properties tend to deteriorate in hightemperature environments, research aimed at improving thermal stability is needed. In this study, a low-temperature plasma annealing process was introduced to improve the high-temperature stability of the a-IGZO thin film. This process enhances electron mobility by reducing defects in the a-IGZO film and provides stable device performance even under high-temperature conditions. As a result of the experiments of 5 min, 10 min, 15 min, and 20 min, the a-IGZO TFT, which was subjected to plasma annealing at 160℃ for 5 min, showed the best electrical performance, especially in charge mobility and current-voltage characteristics. The technical potential for improving the performance of a-IGZO-based display device was emphasized, and the foundation for applying this power generation to flexible displays and next-generation electronic devices was laid. Future research will focus on determining the optimal annealing conditions by exploring various temperature ranges and plasma parameters to integrate these results into the actual device manufacturing process. These efforts are expected advance significantly to advancing next-generation high-performance display technology.

Neuromorphic computing, inspired by the biological mechanisms of neural signal transmission, has emerged as a promising technology for efficient and parallel data processing with minimal power consumption. In this study, we developed floating-gate organic thin-film transistors (OTFTs) with self-assembled monolayer (SAM)-based tunneling layers to mimic the characteristics of artificial synapses. The tunneling layers were formed using mixed phosphonic acid SAMs with varying ratios of octadecylphosphonic acid (ODPA) and 12-pentafluorophenoxydodecylphosphonic acid (PFPA). The influence of these ratios on the memory and neuromorphic characteristics of the devices was systematically evaluated. Our results revealed that the ODPA ratio significantly impacts the hysteresis window, with higher ODPA content yielding improved memory characteristics. Conversely, the PFPA : ODPA ratio of 2:1 exhibited the lowest non-linearity (NL = 0.48), demonstrating the potential for highly accurate weight updates in neuromorphic devices. Additionally, pulse width modulation studies showed that a pulse width of 100 ms optimized the linearity and stability of long-term potentiation (LTP) and depression (LTD) characteristics. The combination of sol-gel processed AlOx as a floating-gate layer and tailored SAM-based tunneling layers allowed for precise control of device performance. These findings highlight the importance of molecular engineering in designing SAM layers to balance memory retention and neuromorphic functionality. This study provides a pathway for advancing organic floating-gate transistors as a core component in next-generation neuromorphic computing systems.

Post-metallization annealing (PMA) has been employed in silicon-based CMOS fabrication to enhance MOSFET reliability and performance. However, although deuterium annealing can reduce interface traps between the Si and SiO₂ gate dielectric, it remains insufficient to fully passivate these traps. In this context, a multiple PMA process, including additional hydrogen annealing, is proposed to further reduce dangling bonds. Silicon-based MOSFETs are fabricated to verify the proposed annealing process architecture. Electrical characterization of the threshold voltage (VTH), subthreshold swing (SS), on-state current (ION), and carrier mobility (μ_n) is conducted to investigate the impact of the multiple PMA. This study provides a guideline for PMA in MOSFET fabrication, with improvements in both performance and reliability.

In this study, the electrical properties of zinc oxide (ZnO) thin-film transistors (TFTs) based on oxide semiconductors were analyzed. As interest in next-generation transparent and flexible displays grows, ZnO, which offers high field-effect mobility and transparency, has emerged as a promising material to overcome the limitations of amorphous silicon (a-Si)-based TFTs. ZnO has a wide bandgap and optical transparency and can be deposited on various substrates at low temperatures, making it a suitable channel material for future display devices. In this study, ZnO TFTs were fabricated with an inverted staggered structure using a p⁺⁺ Si wafer coated with SiO₂ as the substrate. The ZnO channel layer was deposited by RF magnetron sputtering, and the ITO source/drain electrodes were formed using an e-beam evaporator. The electrical characteristics was evaluated using Keithley 4200A-SCS parameter analyzer. Mobility, On/Off ratio, and subthreshold swing (SS) were calculated from the measurements.

The display industry has recently been at the forefront of innovative advancements in modern electronic devices. Technological progress such as flexible display holds significant potential across various application fields, particularly in wearable devices and rollable displays. A low-temperature process is essential for fabricating such displays. One of the key technologies in displays is the thin film transistor (TFT), with amorphous indium gallium zinc oxide (a-IGZO) receiving particular attention. a-IGZO is widely applied in high-performance displays due to its high charge mobility and stability. While a thermal treatment above 350℃ is typically required to maximize the electrical performance of a-IGZO TFTs, such high temperatures pose challenges for utilizing polymer substrates like plastics. Here, we thesis investigates the simultaneous lowtemperature plasma annealing process to develop next-generation high-performance flexible display devices. To define the optimal temperature, devices were fabricated and analyzed at varying temperatures of 40℃, 80℃, 120℃, and 160℃. Experimental results indicated that devices fabricated at 160℃ and 80℃ exhibited superior performance, with those at 160℃ demonstrating better performance in terms of current ratio, threshold voltage, and subthreshold swing. These findings confirm that the simultaneous low-temperature plasma annealing process is effective for next-generation high-performance displays.

This review examines the use of halide perovskite materials in electronic devices, highlighting their exceptional optoelectronic properties and the challenges associated with them. Despite their potential for high-performance devices, practical applications are limited by sensitivity to environmental factors such as moisture and oxygen, etc. We discuss advances in enhancing stability and operational reliability, featuring innovative synthesis methods and device engineering strategies that help mitigate degradation. Furthermore, we explore the integration of perovskites in applications such as field-effect transistors and LEDs, emphasizing their transformative potential. This review also outlines future research directions, stressing the need for ongoing improvements in material stability and device integration to fully realize the commercial potential of perovskites.

Various process modifications have been used to minimize SiO₂ gate oxide aging in metal-oxide-semiconductor field-effect transistors (MOSFETs). In particular, post-metallization annealing (PMA) with a deuterium ambient can effectively eliminate both bulk traps and interface traps in the gate oxide. However, even with the use of PMA, it remains difficult to prevent high levels of radiation-induced gate oxide damage such as total ionizing dose (TID) during long-term missions. In this context, additional low-temperature heat treatment (LTHT) is proposed to recover from radiation-induced damage. Positive traps in the damaged gate oxide can be neutralized using LTHT, thereby prolonging device reliability in harsh radioactive environments.

This study offers a comprehensive evaluation of the role and impact of advanced power semiconductors in solar module systems. Focusing on silicon carbide (SiC) and gallium nitride (GaN) materials, it highlights their superiority over traditional silicon in enhancing system efficiency and reliability. The research underscores the growing industry demand for high-performance semiconductors, driven by global sustainable energy goals. This shift is crucial for overcoming the limitations of conventional solar technology, paving the way for more efficient, economically viable, and environmentally sustainable solar energy solutions. The findings suggest significant potential for these advanced materials in shaping the future of solar power technology.

The size of semiconductor devices has been scaled down to improve packing density and output performance. However, there is uncontrollable spreading of the dopants that comprise the well, punch-stop, and channel-stop when using hightemperature annealing processes, such as rapid thermal annealing (RTA). In this context, low-temperature deuterium annealing (LTDA) performed at a low temperature of 300℃ is proposed to reduce the thermal budget during CMOS fabrication. The LTDA effectively eliminates the interface trap in the gate dielectric layer, thereby improving the electrical characteristics of devices, such as threshold voltage (VTH), subthreshold swing (SS), on-state current (ION), and off-state current (IOFF). Moreover, the LTDA is perfectly compatible with CMOS processes.

The advantage of OTFT technology is that large-area circuits can be manufactured on flexible substrates using a lowcost solution process such as inkjet printing. Compared to silicon-based inorganic semiconductor processes, the process temperature is lower and the process time is shorter, so it can be widely applied to fields that do not require high electron mobility. Materials that have utility as electrode materials include carbon that can be solution-processed, transparent carbon thin films, and metallic nanoparticles, etc. are being studied. Recently, a technology has been developed to facilitate charge injection by coating the surface of the Al electrode with solution-processable titanium oxide (TiOx), which can greatly improve the performance of OTFT. In order to commercialize OTFT technology, an appropriate method is to use a complementary circuit with excellent reliability and stability. For this, insulators and channel semiconductors using organic materials must have stability in the air. In this study, carbon-doped Mo (MoC) thin films were fabricated with different graphite target power densities via unbalanced magnetron sputtering (UBM). The influence of graphite target power density on the structural, surface area, physical, and electrical properties of MoC films was investigated. MoC thin films deposited by the unbalanced magnetron sputtering method exhibited a smooth and uniform surface. However, as the graphite target power density increased, the rms surface roughness of the MoC film increased, and the hardness and elastic modulus of the MoC thin film increased. Additionally, as the graphite target power density increased, the resistivity value of the MoC film increased. In the performance of an organic thin film transistor using a MoC gate electrode, the carrier mobility, threshold voltage, and drain current on/off ratio (I_on/I_off) showed 0.15 cm²/V·s, -5.6 V, and 7.5×10⁴, respectively.

In recent years, the transparent amorphous oxide thin film transistor represented by indium-gallium-zinc-oxide (IGZO) has become the first choice of the next generation of integrated circuit control components. This article contributes an overview of IGZO thin-film transistors (TFTs), including their fundamental principles and recent advancements. The paper outlines various TFT structures and places emphasis on the fabrication process of the active layer. The result showed that the size of the active layer including the length-to-width ratio and the width could have a significant effect on the mobility. And the process of TFT could influence the crystal structure of IGZO thin film. Furthermore, the article presents an overview of recent applications of IGZO TFTs, such as their use in display drivers and TFT memories. At last, the future development of IGZO TFT is forecasted in this paper.

Underwater wireless communication is a challenging issue for realizing the smart aqua-farm and various marine activities for exploring the ocean and environmental monitoring. In comparison to acoustic and radio frequency technologies, the visible light communication is the most promising method to transmit data with a higher speed in complex underwater environments. To send data at a speedier rate, high-performance photodetectors are essentially required to receive blue and/or cyan-blue light that are transmitted from the light sources in a light-fidelity (Li-Fi) system. Here, we fabricated high-performance organic phototransistors (OPTs) based on P-type donor polymer (PTO2) and N-type acceptor small molecule (IT-4F) blend semiconductors. Bulk-heterojunction (BHJ) PTO2:IT-4F photo-active layer has a broad absorption spectrum in the range of 450~550 nm wavelength. Solution-processed OPTs showed a high photo-responsivity >1,000 mA/W, a large photo-sensitivity >10³, a fast response time, and reproducible light-On/Off switching characteristics even under a weak incident light. BHJ organic semiconductors absorbed photons and generated excitons, and efficiently dissociated to electron and hole carriers at the donor-acceptor interface. Printed and flexible OPTs can be widely used as Li-Fi receivers and image sensors for underwater communication and underwater internet of things (UIoTs).

In this work, the effect of sputtering working pressure for the tellurium film and its thin-film transistor was investigated. The transfer characteristics of tellurium thin-film transistors were improved by increasing the working pressure during sputtering process. As increasing working pressure, physical and optical properties of Te films such as crystallinity, transmittance, and surface roughness were improved. Therefore, the improved transfer characteristics of Te thin-film transistors may originate from both improved interface properties between the silicon oxide gate dielectric layer and the tellurium active layer with an improved quality of Te film. In conclusion, the control of working pressure during sputtering would be important for obtaining highperformance tellurium-based thin film transistor.

TFTs technologies with as high mobility as possible is essential for high-performance large displays. TFTs using nanocrystalline silicon thin films can achieve higher mobility. In this work, the change of the crystalline volume fraction at different hydrogen dilution ratios was investigated by depositing nc-Si:H thin films using PECVD. It was observed that increasing hydrogen dilution ratio increased not only the crystalline volume fraction but also the crystallite size. The thin films with a high crystalline volume fraction (55%) and a low defect density (10¹⁷ cm^-3·eV^-1) were used as top gate TFTs channel layer, leading to a high mobility (55 ㎠/V·s). We suggest that TFTs of high mobility to meet the need of display industries can be benefited by the formation of thin film with high crystalline volume fraction as well as low defect density as a channel layer.

The transfer characteristics of amorphous indium gallium zinc oxide thin film transistor (a-IGZO TFT) showed the distortion in the subthreshold region after gate bias stress, in addition to the parallel shift of threshold voltage. The capacitancevoltage (C-V) curve was also deformed from its initial shape after the gate bias stress. This study analyzes both the C-V and transfer curves plotted on the same gate voltage axis in order to investigate the mechanism driving the distortion in the transfer curve. It is deduced that an additional interfacial trap states at the bottom interface of a-IGZO are produced during gate bias stress, thereby they exhibit the back channel effect, which explains the origin of the distortion in the transfer curve and the deformation of C-V curve.

Focused electron beams with high energy acceleration are versatile probes. Focused electron beams can be used for high-resolution imaging and multi-mode nanofabrication, in combination with, molecular precursor delivery, in an electron microscopy environment. A high degree of control with atomic-to-microscale resolution, a focused electron beam allows for precise engineering of a graphene-based field-effect transistor (FET). In this study, the effect of electron irradiation on a graphene FET was systematically investigated. A separate evaluation of the electron beam induced transport properties at the graphene channel and the graphene-metal contacts was conducted. This provided on-demand strategies for tuning transfer characteristics of graphene FETs by focused electron beam irradiation.

We investigated the effect of a post-annealing process using ultraviolet (UV) light on the electrical properties of solution-processed InZnO (IZO) thin-film transistors (TFTs). UV light was irradiated on IZO TFTs for different time periods of 0s, 30s, and 90s. We measured transfer and retention stability curves to evaluate the performance of the fabricated TFTs. In addition, we measured height, amplitude, and phase AFM images to analyze changes in the surface and morphology of the devices. AFM measurements were performed by setting the drive amplitude of the cantilever tip to 47.9 mV in tapping mode, then dividing the device surface into 500 nm × 500 nm. In the case of IZO TFT irradiated with UV for 30s, the electron mobility and Ion/Ioff ratio were improved, the threshold voltage was reduced by approximately 2 V, and the subthreshold swing also decreased form 1.34 V/dec to 1.11 V/dec.

In this paper, a single N+ emitter trench gate-type insulated gate bipolar transistor (IGBT) device was studied using T-CAD, in order to achieve a low on-state voltage drop (Vce-sat) and high breakdown voltage, which would reduce power loss and device reliability. Using the simulation, the threshold voltage, breakdown voltage, and on-state voltage drop were studied as a function of the temperature, the length of time in the diffusion process (drive-in) after implant, and the trench gate depth. During the drive-in process, a 20℃ change in temperature from 1,000 to 1,160℃ over a 150 minute time frame resulted in a 1 to 4 V change in the threshold voltage and a 24 to 2.6 V change in the on-state voltage drop. As a result, a 0.5 um change in the trench depth of 3.5 to 7.5 um resulted in the breakdown voltage decreasing from 802 to 692 V.

Developing a thin-film transistor with characteristics such as a large area, high mobility, and high reliability are key elements required for the next generation on displays. In this paper, we have investigated the research trends related to improving the reliability of oxide-semiconductor-based thin-film transistors, which are the primary focus of study in the field of optical displays. It has been reported that thermal treatment in a high-pressure oxygen atmosphere reduces the threshold voltage shift from -7.1 V to -1.9 V under NBIS. Additionally, a device with a SiO₂/Si₃N₄ dual-structure has a lower threshold voltage (-0.82 V) under NBIS than a single-gate-insulator-based device (-11.6 V). The dual channel structure with different oxygen partial pressures was also confirmed to have a stable threshold voltage under NBIS. These can be considered for further study to improve the NBIS problem.

We investigated the electrical characteristics of amorphous silicon-zinc-tin-oxide (a-SZTO) thin films deposited by RF-magnetron sputtering at room temperature depending on the deposition time. We fabricated a thin film transistor (TFT) with a bottom gate structure and various channel thicknesses. With increasing channel thickness, the threshold voltage shifted negatively from -0.44 V to -2.18 V, the on current (I_on) and field effect mobility (μFE) increased because of increasing carrier concentration. The a-SZTO film was fabricated and analyzed in terms of the contact resistance and channel resistance. In this study, the transmission line method (TLM) was adopted and investigated. With increasing channel thickness, the contact resistance and sheet resistance both decreased.

This report constitutes the first demonstration in Korea of single-crystal lateral gallium oxide (Ga₂O₃) as a metal-oxide-semiconductor field-effect-transistor (MOSFET), with a breakdown voltage in excess of 480 V. A Si-doped channel layer was grown on a Fe-doped semi-insulating β-Ga₂O₃ (010) substrate by molecular beam epitaxy. The single-crystal substrate was grown by the edge-defined film-fed growth method and wafered to a size of 10×15 mm². Although we fabricated several types of power devices using the same process, we only report the characterization of a finger-type MOSFET with a gate length (L_g) of 2 μm and a gate-drain spacing (L_gd) of 5 μm. The MOSFET showed a favorable drain current modulation according to the gate voltage swing. A complete drain current pinch-off feature was also obtained for V_gs<-6 V, and the three-terminal off-state breakdown voltage was over 482 V in a L_gd＝5 μm device measured in Fluorinert ambient at V_gs＝-10 V. A low drain leakage current of 4.7 nA at the off-state led to a high on/off drain current ratio of approximately 5.3×10⁵. These device characteristics indicate the promising potential of Ga₂O₃-based electrical devices for next-generation high-power device applications, such as electrical autonomous vehicles, railroads, photovoltaics, renewable energy, and industry.

This research introduces the sputtered IZO thin film transistor (TFT) with solution-processed Al₂O₃ diffusion layer. IZO is one of the most commonly used amorphous oxide semiconductor (AOS) TFT. However, most AOS TFTs have many defects that degrade performance. Especially oxygen vacancy in the active layer. In previous research, aluminum was used as a carrier suppressor by binding the oxygen vacancy and making a strong bond with oxygen atoms. In this paper, we use a solution-processed Al₂O₃ diffusion layer to fabricate stable IZO TFTs. A double-layer solution-processed Al2O3-sputtered IZO TFT showed better performance and stability, compared to normal sputtered IZO TFT.

Herein, we report the manufacture of high-performance, ambipolar organic field-effect transistors (OFETs) and complementary-like electronic circuitry based on a blended, polymeric, semiconducting film. Relatively high and wellbalanced electron and hole mobilities were achieved by incorporating a small amount of ionic additives. The equivalent P-channel and N-channel properties of the ambipolar OFETs enabled the manufacture of complementary-like inverter circuits with a near-ideal switching point, high gain, and good noise margins, via a simple blanket spin-coating process with no additional patterning of each active P-type and N-type semiconductor layer.

The computational fourier-transform moire (CFTM) method has been briefly explained and this method was used to perform strain analysis of a misfit dislocation in a strained Si/Si_0.55Ge_0.45 layer. An essential advantage of the CFTM method is that it does not require unwrapping, such that errors due to improper unwrapping can be excluded. The analysis results revealed that the Si layer was grown with tensile stress on Si_0.55Ge_0.45 and lattice constant of the Si layer along the growth direction was 1.9% smaller than that of Si_0.55Ge_0.45. On the other hand, strain of the misfit dislocation in the strained Si/Si_0.55Ge_0.45 layer was maximum at the dislocation core due to an extra half-plane and the e_xx and e_yy values were positive and negative, respectively, along the direction of a burgers vector.

Herein, we report the fabrication of low-voltage N-type organic field-effect transistors by using high capacitance fluorinated polymer gate dielectrics such as P(VDF-TrFE), P(VDF-TrFE-CTFE), and P(VDF-TrFE-CFE). Electronwithdrawing functional groups in PVDF-based polymers typically cause the depletion of negative charge carriers and a high contact resistance in N-channel organic semiconductors. Therefore, we incorporated intermediate layers of a low-k polymerto prevent the formation of a direct interface between PVDF-based gate insulators and the semiconducting active layer. Consequently, electron depletion is inhibited, and the high charge resistance between the semiconductor and source/drain electrodes is remarkably improved by the in corporation of solution-processed charge injection layers.

A soft baking process was used to enhance the electrical characteristics of solution-processed indium-zincoxide (IZO) thin-film transistors (TFTs). We demonstrate a stable soft baking process using a hot plate in air to maintain the electrical stability and improve the electrical performance of IZO TFTs. These oxide transistors exhibited good electrical performance; a field-effect mobility of 7.9 cm²/Vs, threshold voltage of 1.4 V, sub-threshold slope of 0.5 V/dec, and a current on/off ratio of 2.9×10⁷ were measured. To investigate the static response of our solutionprocessed IZO TFTs, simple resistor load type inverters were fabricated by connecting a resistor (5 or 10 MΩ). Our IZO TFTs, which were manufactured using the soft baking process at a baking temperature of 120℃, performed well at the operating voltage, and are therefore a good candidate for use in advanced logic circuits and transparent display backplanes.