In this work, we investigate the effects of lithium doping on the electric performance of solution-processed n-type zinc tin oxide (ZTO)/p-type silicon carbide (SiC) heterojunction diode structures. The proper amount of lithium doping not only affects the carrier concentration and interface quality but also influences the temperature sensitivity of the series resistance and activation energy. We confirmed that the device characteristics vary with lithium doping at concentrations of 0, 10, and 20 wt%. In particular, the highest rectification ratio of 1.89×107 and the lowest trap density of 4.829×1,022 cm^-2 were observed at 20 wt% of lithium doping. Devices at this doping level showed the best characteristics. As the temperature was increased, the series resistance value decreased. Additionally, the activation energy was observed to change with respect to the component acting on the trap. We have demonstrated that lithium doping is an effective way to obtain a higher performance ZTO-based diode.

We have investigated the effect of electrical properties of amorphous InGaZnO thin filmtransistors (a-IGZO TFTs) by post thermal annealing in O2 ambient.The post-annealed in O2 ambienta-IGZOTFT is found to be more stable to be used for oxide-based TFT devices, and has betterperformance, such as the on/off current ratios, sub-threshold voltage gate swing, and, as well asreasonable threshold voltage, than others do. The interface trap density is controlled to achieve theoptimum value of TFT transfer and output characteristics. The device performance is significantlyaffected by adjusting the annealing condition. This effect is closely related with the modulation annealingmethod by reducing the localized trapping carriers and defect centers at the interface or in the channellayer.

In this paper, we investigated an anomalous hump phenomenon under the positive bias stress in p-type LTPS TFTs. The devices with inferior electrical performance also show larger hump phenomenon. which can be explained by the sub-channel induced from trapped electrons under thinner gate oxide region. We can confirm that the devices with larger hump have larger interface trap density (Dit) and grain boundary trap density (Ntrap) extracted by low-high frequency capacitance method and Levinson-Proano method, respectively. From the C-V with I-V transfer characteristics, the trapped electrons causing hump seem to be generated particularly from the S/D and gate overlapped region. Based on these analysis, the major cause of an anomalous hump phenomenon under the positive bias stress in p-type poly-Si TFTs is explained by the GIDL occurring in the S/D and gate overlapped region and the traps existing in the channel edge region where the gate oxide becomes thinner, which can be inferred by the fact that the magnitude of the hump is dependent on the average trap densities.

Recently, amorphous oxide semiconductors (AOSs) based thin-film transistors (TFTs) have received considerable attention for application in the next generation displays industry. The research trends of AOSs based TFTs investigation have focused on the high device performance. The electrical properties of the TFTs are influenced by trap density. In particular, the threshold voltage (Vth) and subthreshold swing (SS) essentially depend on the semiconductor/gate-insulator interface trap. In this article, we investigated the effects of Ar plasma-treated SiO2 insulator on the interfacial property and the device performances of amorphous indium gallium zinc oxide (a-IGZO) TFTs. We report on the improvement in interfacial characteristics between a-IGZO channel layer and gate insulator depending on Ar power in plasma process, since the change of treatment power could result in different plasma damage on the interface.