Wearable temperature sensors are becoming increasingly important for continuous health monitoring, personalized healthcare, and biointegrated electronic systems. However, conventional temperature-sensing platforms often suffer from limited thermal sensitivity, insufficient mechanical compliance, and unstable performance under repeated deformation, making it difficult to detect subtle physiological temperature variations in real time. Here, this tutorial status report presents a fabrication strategy for highly sensitive wearable temperature sensors based on gold-doped crystalline silicon nanomembranes. Gold diffusion into crystalline silicon introduces deep-level impurity states that modulate the Fermi level and shift the freeze-out region toward the physiological temperature range, enabling an ultrahigh negative temperature coefficient of resistance. By integrating the gold-doped silicon nanomembrane with a polyimide-supported ultrathin platform, neutral mechanical plane design, and serpentine mesh interconnects, the resulting device can provide high thermal sensitivity, fast response, conformal skin attachment, and stable operation under mechanical deformation. This fabrication approach is expected to broaden the use of impurity-engineered silicon nanomembranes in next-generation wearable sensors, flexible bioelectronics, and multifunctional healthcare monitoring systems.
This study investigates the effect of mask material and thickness on the silicon etching profile using a high-density plasma (HDP) etching system, aiming to reduce optical loss in silicon-based optical waveguides. As the mask thickness increased, the etching sidewall angle became steeper. An etching profile angle of 87° was obtained when tetraethyl orthosilicate (TEOS) was used as the mask material, while 80° was obtained for photoresist (PR). This is attributed to electron charging on the mask surface in the plasma. The charged mask modifies the distribution and strength of the electric field depending on its thickness, thereby affecting the trajectory of positive ions accelerated toward the substrate by the bias voltage. Furthermore, Plasma diagnostics using optical emission spectroscopy (OES) and surface composition analysis using field emission Auger electron spectroscopy (FE-AES) revealed that changes in the mask material also alter the reaction pathways and formation characteristics of active species and silicon by-products in the plasma. These results suggest that the mask material influences the overall plasma characteristics, including electron density and ion energy, and plays a critical role in the precise control of silicon etching profiles for high-performance optical device fabrication.
Silicon carbide (SiC), with its wide bandgap and strong resistance to radiation and thermal conditions, is a promising material for ultraviolet (UV) photodetector applications under harsh environments. In this study, porous SiC thin films with thicknesses of 20, 50, and 80 nm were fabricated on 4H-SiC substrates using aerosol deposition (AD), which enables roomtemperature film formation. The device with a 50 nm-thick film exhibited the highest photoresponse under UV-C illumination (260 nm), achieving a maximum photo-to-dark current ratio (PDCR) of 205.2, a responsivity of 0.058 A/W, an external quantum efficiency (EQE) of 27.71%, and a specific detectivity (D*) of 7.9×1011 Jones. These results are attributed to an optimized balance between photon absorption and carrier transport in the porous structure. The findings confirm the potential of ADfabricated porous SiC films for highly sensitive and scalable UV photodetector applications.
Beom Jin Kim, Pil Hong Jeong, Jae Min Lee, Dong Hwan Won, Jeong Ho Lee, Heon Min Lee, Ku Yun Jeong, Keon Park, Kawan Anil, Soon Jae Yu, Yeon Sik Chae, Sung Bae Park
J Electr Electron Mater 2025;38(3):272-277. Published online May 1, 2025
SMD-type 660 nm wavelength semiconductor laser diode device is fabricated using silicon resin molding technology and fabricated a BT resin printed circuit board. BT resin electrode structure printed circuit boards with soldering electrode pads and through holes for heat dissipation were fabricated. The SMD process is an injection molding technique in which the chip is molded from silicon material and then cut by a dicing process to complete the beam emission surface. The fabricated SMD-type semiconductor laser diode exhibits a good near-field beam pattern with no scattering/dispersion caused by the printed circuit board or silicon molding in the emitted laser beam, or reflections around the chip. It was also confirmed that the heat generated at 20 mA operation has good heat dissipation characteristics through the through-hole heat dissipation structure.
Post-metallization annealing (PMA) has been employed in silicon-based CMOS fabrication to enhance MOSFET reliability and performance. However, although deuterium annealing can reduce interface traps between the Si and SiO₂ gate dielectric, it remains insufficient to fully passivate these traps. In this context, a multiple PMA process, including additional hydrogen annealing, is proposed to further reduce dangling bonds. Silicon-based MOSFETs are fabricated to verify the proposed annealing process architecture. Electrical characterization of the threshold voltage (VTH), subthreshold swing (SS), on-state current (ION), and carrier mobility (μn) is conducted to investigate the impact of the multiple PMA. This study provides a guideline for PMA in MOSFET fabrication, with improvements in both performance and reliability.
We investigated the potential of IO:H thin films and hydrogen doping to improve current density and fill factor for enhancing the performance of silicon heterojunction solar cells. We revealed that a transmittance of 86.7% and work function of 5.4 eV could be achieved by injecting 3 sccm of hydrogen gas. The lattice constant of 1.037 nm at the AB site indicates an anion antibonding tendency, and the work function increases as the Fermi level shifts to the valence band. Based on these findings, we fabricated a silicon heterojunction solar cell and achieved an efficiency of 18.53%, while computer simulation confirmed a conversion efficiency of 24.65%, an open-circuit voltage of 724 mV, and a fill factor of 82.72% at a current density of 41.15 mA/㎠.
This study investigates the post-thermal treatment effects on the efficiency of silicon heterojunction solar cells, specifically examining the influence of annealing on p-type microcrystalline silicon oxide and ITO thin films. By assessing changes in carrier concentration, mobility, resistivity, transmittance, and optical bandgap, we identified conditions that optimize these properties. Results reveal that appropriate annealing significantly enhances the fill factor and current density, leading to a notable improvement in overall solar cell efficiency. This research advances our understanding of thermal processing in siliconbased photovoltaics and provides valuable insights into the optimization of production techniques to maximize the performance of solar cells.
The low-temperature coefficient of resistance (TCR) is a crucial factor in the development of space-grade resistors for temperature stability. Consequently, extensive research is underway to achieve zero TCR. In this study, resistors were deposited by co-sputtering nickel-chromium-based composite compositions, metals showing positive TCR, with SiO2, introducing negative TCR components. It was observed that achieving zero TCR is feasible by adjusting the proportion of negative TCR components in the deposited thin film resistors within certain compositions. Additionally, the correlation between TCR and deposition conditions, such as sputtering power, Ar pressure, and surface roughness, was investigated. We anticipate that these findings will contribute to the study of resistors with very low TCR, thereby enhancing the reliability of space-level resistors operating under high temperatures.
The size of semiconductor devices has been scaled down to improve packing density and output performance. However, there is uncontrollable spreading of the dopants that comprise the well, punch-stop, and channel-stop when using hightemperature annealing processes, such as rapid thermal annealing (RTA). In this context, low-temperature deuterium annealing (LTDA) performed at a low temperature of 300℃ is proposed to reduce the thermal budget during CMOS fabrication. The LTDA effectively eliminates the interface trap in the gate dielectric layer, thereby improving the electrical characteristics of devices, such as threshold voltage (VTH), subthreshold swing (SS), on-state current (ION), and off-state current (IOFF). Moreover, the LTDA is perfectly compatible with CMOS processes.
The purpose of this paper is to help those who research and develop solar cells in university laboratories and industrial sites understand the most basic and important quantum efficiency measurement and analysis method in analyzing solar cell performance. Starting with the definition of quantum efficiency, we calculate the theoretical current density according to the band gap of the solar cell material from the solar spectrum, along with a detailed introduction to the measurement and analysis methods, and measure and analyze the theoretical current density and quantum efficiency. We discuss in depth how to analyze the performance of solar cells through Quantum efficiency measurement and analysis of solar cells is a very useful method that can give intuition to solar cell performance analysis as it can analyze solar cells according to depth (front emitter, bulk, rear surface). Students and researchers who study solar cells with a deep understanding of theoretical current density and quantum efficiency measurement analysis are expected to use it as a basis for analyzing solar cell performance.
Crystalline silicon solar cells have attracted great attention for their various advantages, such as the availability of raw materials, high-efficiency potential, and well-established processing sequence. Tunnel oxide passivated contact (TOPCon) solar cells are widely regarded as one of the most prospective candidates for the next generation of high-performance solar cells because an efficiency of 26% has been achieved in small-area solar cells. Compared to n-type TOPCon solar cells, the photo conversion efficiency (PCE) of p-type TOPCon is slightly higher. The highest PCEs of p-type TOPCon and n-type TOPCon solar cells are 26.0% and 25.8%, respectively. Despite the highest efficiency in small-area cells, limited progress has been achieved in p-type TOPCon solar cells for large are due to their lower carrier lifetime and inferior surface passivation with the boron-doped c-Si wafer. Nevertheless, it is of great importance to promoting the p-type TOPCon technology due to its lower price and well-established manufacturing procedures with slight modifications in the PERC solar cells production lines. The progress in different approaches to increase the efficiencies of p-type TOPCon solar cells has been reported in this review article and is expected to set valuable strategies to promote the passivation technology of p-type TOPCon, which could further increase the efficiency of TOPCon solar cells.
p-type Tunnel Oxide Passivating Contacts (TOPCon) solar cell is fabricated with a poly-Si/SiOx structure. It simultaneously achieves surface passivation and enhances the carriers’ selective collection, which is a promising technology for conventional solar cells. The quality of passivation is depended on the quality of the tunnel oxide layer at the interface with the c-Si wafer, which is affected by the bond of SiO formed during the subsequent annealing process. The highest cell efficiency reported to date for the laboratory scale has increased to 26.1%, fabricated by the Institute for Solar Energy Research. The cells used a p-type float zone silicon with an interdigitated back contact (IBC) structure that fabricates poly-Si and SiOx layer achieves the highest implied open-circuit voltage (iVoc) is 750 mV, and the highest level of edge passivation is 40%. This review presents an overview of p-type TOPCon technologies, including the ultra-thin silicon oxide layer (SiOx) and poly-silicon layer (poly-Si), as well as the advancement of the SiOx and poly-Si layers. Subsequently, the limitations of improving efficiency are discussed in detail. Consequently, it is expected to provide a basis for the simplification of industrial mass production.
This paper demonstrates a novel NAND flash memory structure and annealing configuration including through-silicon via (TSV) inside the silicon substrate to improve annealing efficiency using an electro-thermal annealing (ETA) technique. Compared with the conventional ETA which utilizes WL-to-WL current flow, the proposed annealing method has a higher annealing temperature as well as more uniform heat distribution, because of thermal isolation on the silicon substrate. In addition, it was found that the annealing temperature is related to the electrical and thermal conductivity of the TSV materials. As a result, it is possible to improve the reliability of NAND flash memory. All the results are discussed based on 3-dimensional (3-D) simulations with the aid of the COMSOL simulator.
In this study, we measured and comparatively analyzed the characteristics of MPS (Merged Pin Schottky) diodes in 4H-SiC by changing the areal ratio between the Schottky and PN junction region. Increasing the temperature from 298 K to 473 K resulted in the threshold voltage shifting from 0.8 V to 0.5 V. A wider Schottky region indicates a lower on-resistance and a faster turn-on. The effective barrier height was smaller for a wider Schottky region. Additionally, the depletion layer became smaller under the influence of the reduced effective barrier height. The wider Schottky region resulted in the ideality factor being reduced from 1.37 to 1.01, which is closer to an ideal device. The leakage saturation current increased with the widening Schottky region, resulting in a 1.38 times to 2.09 times larger leakage current.
As the demand for new and renewable energy increases due to the depletion of fossil fuels, solar power generation, a core energy source for new and renewable energy, requires research on solar modules for high output power generation. In this paper, the electrical characteristics of solar cell strip at the edge and in the center of single-crystal silicon having a semi-square shape were analyzed. The cell strip located in the center showed the efficiency increase by 0.26% compared to the cell strip at the edge of the solar cell. A shingled photovoltaic module was manufactured for each cell strip. As a result, the output power of the module using the cell strip located in the center was higher by 0.992%.
a-Si is commonly considered as a primary candidate for the formation of passivation layer in heterojunction (HIT) solar cells. However, there are some problems when using this material such as significant losses due to recombination and parasitic absorption. To reduce these problems, a wide bandgap material is needed. A wide bandgap has a positive influence on effective transmittance, reduction of the parasitic absorption, and prevention of unnecessary epitaxial growth. In this paper, the adoption of a-SiOx:H as the intrinsic layer was discussed. To increase lifetime and conductivity, oxygen concentration control is crucial because it is correlated with the thickness, bonding defect, interface density (Dit), and band offset. A thick oxygenrich layer causes the lifetime and the implied open-circuit voltage to drop. Furthermore the thicker the layer gets, the more free hydrogen atoms are etched in thin films, which worsens the passivation quality and the efficiency of solar cells. Previous studies revealed that the lifetime and the implied voltage decreased when the a-SiOx thickness went beyond around 9 nm. In addition to this, oxygen acted as a defect in the intrinsic layer. The Dit increased up to an oxygen rate on the order of 8%. Beyond 8%, the Dit was constant. By controlling the oxygen concentration properly and achieving a thin layer, high-efficiency HIT solar cells can be fabricated.
TFTs technologies with as high mobility as possible is essential for high-performance large displays. TFTs using nanocrystalline silicon thin films can achieve higher mobility. In this work, the change of the crystalline volume fraction at different hydrogen dilution ratios was investigated by depositing nc-Si:H thin films using PECVD. It was observed that increasing hydrogen dilution ratio increased not only the crystalline volume fraction but also the crystallite size. The thin films with a high crystalline volume fraction (55%) and a low defect density (1017 cm-3·eV-1) were used as top gate TFTs channel layer, leading to a high mobility (55 ㎠/V·s). We suggest that TFTs of high mobility to meet the need of display industries can be benefited by the formation of thin film with high crystalline volume fraction as well as low defect density as a channel layer.
In this work, we fabricated oxide on an n-type silicon substrate through local anodic oxidation (LAO) using atomic force microscopy (AFM). The resulting oxide thickness was measured and its correlation with load force, scan speed and applied voltage was analyzed. The surface oxide layer was stripped using a buffered oxide etch. Ohmic contacts were created by applying silver paste on the silicon substrate back face. LAO was performed at approximately 70% humidity. The oxide thickness increased with increasing the load force, the voltage, and reducing the scan speed. We confirmed that LAO/AFM can be used to create both lateral and, to some extent, vertical shapes and patterns, as previously shown in the literature.
We present a subthreshold swing model for a symmetric junctionless double gate MOSFET. The scale length λ1 required to obtain the potential distribution using the Poisson's equation is a criterion for analyzing the short channel effect by an analytical model. In general, if the channel length Lg satisfies Lg ＞ 1.5λ1, it is known that the analytical model can be sufficiently used to analyze short channel effects. The scale length varies depending on the channel and oxide thickness as well as the dielectric constant of the channel and the oxide film. In this paper, we obtain the scale length for a constant permittivity (silicon and silicon dioxide), and derive the relationship between the scale length and the channel length satisfying the error range within 5%, compared with a numerical method. As a result, when the thickness of the oxide film is reduced to 1 nm, even in the case of Lg ＜ λ1, the analytical subthreshold swing model proposed in this paper is observed to satisfy the error range of 5%. However, if the oxide thickness is increased to 3 nm and the channel thickness decreased to 6 nm, the analytical model can be used only for the channel length of Lg ＞ 1.8 λ1.
Modern thin film deposition processes require high deposition rates, low costs, and high-quality films. Atmospheric pressure plasma-enhanced chemical vapor deposition (AP-PECVD) meets these requirements. AP-PECVD causes little damage on thin film deposition surfaces compared to conventional PECVD. Moreover, a higher deposition rate is expected due to the surface heating effect of atomic hydrogens in AP-PECVD. In this study, polycrystalline silicon thin film was deposited at a low temperature of 100℃ and then AP-PECVD experiments were performed with various plasma powers and hydrogen gas flow rates. A deposition rate of 15.2 nm/s was obtained at the VHF power of 400 W. In addition, a metal foam showerhead was employed for uniform gas supply, which provided a significant improvement in the thickness uniformity.
Grain boundaries play a major role in determining device performance, particularly of polysilicon-based photodetectors. Through the post-annealing of as-deposited polysilicon and then, the analysis of electric behavior for a metal-polysilicon-metal (MSM) photodetector, we were able to identify the influence of grain boundaries. A modified model of polysilicon grain boundaries in the MSM structure is presented, which uses a crystalline-interfacial layer-SiOx layer- interfacial layer-crystalline system that is similar to the Si-SiO2 system in MOS device. Hydrogen passivation was achieved through a hydrogen ion implantation process and was used to passivate the defects at both interfacial layers. The thin SiOx layer at the grain boundary can enhance the photosensitivity of an MSM photodetector by decreasing the dark current and increasing the light absorption.
The wettability of silicon carbide (SiC) crystal, which has 6H-SiC and 4H-SiC regions prepared using the physical vapor transport (PVT) method, is quantitatively analyzed using dispensed deionized (DI) water droplets. Regardless of the polytypes in SiC, the average of five contact angle measurements showed a difference of about 6° between the Si-face and C-face. The contact angle on the Si-face (C-face) is measured after the removal of the native oxide using BOE (6:1), and revealed a significant decrease of the contact angle from 74.9° (68.4°) to 47.7° (49.3°) and from 75.8° (70.2°) to 51.6° (49.5°) for the 4H-SiC and 6H-SiC regions, respectively. The contact angle of the Si-face recovered over time during room temperature oxidation in air; in contrast, that of the C-face did not recover to the initial value. This study shows that the contact angle is very sensitive to SiC surface polarity, specific surface conditions, and process time. Contact angle measurements are expected to be a rapid way of determining the surface polarity and wettability of SiC crystals.
Ga2O3/n-type 4H-SiC heterojunction diodes were fabricated by RF magnetron sputtering. The optical properties of Ga2O3 and electrical properties of diodes were investigated. I-V characteristics were compared with simulation data from the Atlas software. The band gap of Ga2O3 was changed from 5.01 eV to 4.88 eV through oxygen annealing. The doping concentration of Ga2O3 was extracted from C-V characteristics. The annealed oxygen exhibited twice higher doping concentration. The annealed diodes showed improved turn-on voltage (0.99 V) and lower leakage current (3 pA). Furthermore, the oxygen-annealed diodes exhibited a temperature cross-point when temperature increased, and its ideality factor was lower than that of as-grown diodes.
A fire, be it caused intentionally or unintentionally, leads to economic loss and physical damage, and requires digestion. The number of fires is increasing yearly, and electrical fires account for more than 30% among the main causes of fires. Electric wires that catch fire typically employ silicone coatings; silicone has organic as well as inorganic properties. Silicon is a natural, nonexistent, synthetic product with numerous applications. In this study, a silicon rubber for application in wires was prepared by high-temperature vulcanization (HTV) with a Shore A hardness of 70. We report results for the flame retardancy test and the fire safety characteristics via inorganic analysis. For this, a quartz inorganic material was added to the wire specimen, and 18% powdered extinguishing agent ammonium phosphate and expanded vermiculite respectively. Thus, expanded vermiculite showed the best flame retardancy and fire safety characteristics.
In this study, a high-temperature vulcanizing (HTV) method was used to achieve a shore a hardness of 70. The basic base was composed of 60% silicon gum (GUM) which is a high-viscosity polymer, 30% fumed silica (FS), and 5% of plasticizer. The GUM and FS were mixed well with less than 1% silane to improve rubber strength. Expanded vermiculite was added as a filler at 10%, 15%, and 20%. The curing conditions were 170℃ for 10 min and a molding method was applied. We report herein, the results of inorganic analysis and flame-retardant and tracking tests on the expanded vermiculite. The flame retardance and tracking test outcomes for a shore a hardness of 70 were found to be optimal when the expanded vermiculite content was 10%.
The change in vanadium amount according to the growth direction of vanadium-doped semi-insulated (SI) SiC single crystals using high-purity SiC powder was investigated. High-purity SiC powder and a porous graphite (PG) inner crucible were placed on opposite sides of SiC seed crystals. SI SiC crystals were grown on 2 inch 6H-SiC Si-face seeds at a temperature of 2,300℃ and growth pressure of 10~30 mbar of argon atmosphere, using the physical vapor transport (PVT) method. The sliced SiC single crystals were polished using diamond slurry. We analyzed the polytype and quality of the SiC crystals using high-resolution X-ray diffraction (XRD) and Raman spectroscopy. The resistivity of the SI SiC crystals was analyzed using contactless resistivity mapping (COREMA) measurements.
Hexagonal boron nitride particles (s-hBN) modified with 3-aminopropyl triethoxysilane (APTES) were used for the preparation of silicone composite materials. The microstructure of the composite materials was observed, and the thermal conduction and mechanical characteristics of the composite sheets were studied based on the compositions and microstructures. When a small amount of s-hBN particles was used, the thermal conductivity of the composite improved as a whole, and the tensile strength of the sheet also increased. The thermal conductivity and tensile strength of the composite in which a small amount of carbon fiber was added along with s-hBN were further improved. However, the use of carbon nanotubes with structural characteristics similar to those of carbon fiber resulted in lower thermal conductivity and tensile strength. Elastic silicone composites exhibiting 2.5 W/mK of thermal conductivity and a low hardness are expected to be used as thermally conductive interfacial sheet materials.
1,200 V class junction barrier schottky (JBS) diodes and schottky barrier diodes (SBD) were simultaneously fabricated on the same 4H-SiC wafer. The resulting diodes were characterized at temperatures from room temperature to 473 K and subsequently compared in terms of their respective I-V characteristics. The parameters deduced from the observed I-V measurements, including ideality factor and series resistance, indicate that, as the temperature increases, the threshold voltage decreases whereas the ideality factor and barrier height increase. As JBS diodes have both Schottky and PN junction structures, the proper depletion layer thickness, Ron, and electron mobility values must be determined in order to produce diodes with an effective barrier height. The comparison results showed that the JBS diodes exhibit a larger effective barrier height compared to the SBDs.
SiGe thin films were deposited by remote plasma enhanced chemical vapor deposition (RPE-CVD) at 400℃ using SiH4 or SiCl4 and GeCl4 as the source of Si and Ge, respectively. The growth rate and the degree of crystallinity of the fabricated films were characterized by scanning electron microscopy and Raman analysis, respectively. The optical and electrical properties of SiGe films fabricated using SiCl4 and SiH4 source were comparatively studied. SiGe films deposited using SiCl4 source showed a lower growth rate and higher crystallinity than those deposited using SiH4 source. Ultraviolet and visible spectroscopy measurement showed that the optical band gap of SiGe is in the range of 0.88~1.22 eV.
In order to achieve a high efficiency for the silicon solar cell, a passivation characteristic that minimizes the electrical loss at a silicon interface is required. In this paper, we evaluated the applicability of the oxide film formed by ozone for the tunnel silicon oxide film. To this end, we fabricated the silicon oxide film by changing the condition of ozone oxidation and compared the characteristics with the oxide film formed by the existing nitric acid solution. The ozone oxidation was formed in the temperature range of 300~500℃ at an ozone concentration of 17.5 wt%, and the passivation characteristics were compared. Compared to the silicon oxide film formed by nitric acid oxidation, implied open circuit voltage (iVoc) was improved by ~20 mV in the ozone oxidation and the ozone oxidation after the nitric acid pretreatment was improved by ~30 mV.
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