The rapid advancement of large-scale language models and artificial intelligence technologies has highlighted the importance of data processing efficiency. This study outlines a measurement optimization method for high-speed pulse equipment to accurately analyze the operating dynamics of ReRAM, a core hardware component for simulating neural networks. An optimized evaluation methodology combining connection compensation and a dual-channel configuration was established to minimize measurement errors caused by parasitic resistance and capacitance during pulse measurements using the Keithley 4200A-SCS and 4225-PMU modules, and to address HRS/LRS measurement errors caused by mismatches between the measurement range and source limits. The proposed precision measurement guidelines can be applied to the evaluation of semiconductor devices that require pulse measurements, such as transistors and DRAM.
To evaluate the possibility as a multi-level memory medium for the Ge2Sb2Te5/TiN/W-doped Ge2Sb2Te5 cell structure, the crystallization rate and stabilization characteristics according to voltage (V)- and current (I)- pulse sweeping were investigated. In the cell structures prepared by a magnetron sputtering system on a p-type Si (100) substrate, the Ge2Sb2Te5 and W-doped Ge2Sb2Te5 thin films were separated by a barrier metal, TiN, and the individual thicknesses were varied, but the total thickness was fixed at 200 nm. All cell structures exhibited relatively stable multi-level states of high-middle-low resistance (HR-MR-LR), which guarantee the reliability of the multilevel phase-change random access memory (PRAM). The amorphousto- multilevel crystallization rate was evaluated from a graph of resistance (R) vs. pulse duration (T) obtained by the nanoscaled pulse sweeping at a fixed applied voltage (12 V). For all structures, the phase-change rates of HR→MR and MR→LR were estimated to be approximately t<20 ns and t<40 ns, respectively, and the states were relatively stable. We believe that the doublestack structure of an appropriate Ge-Sb-Te film separated by barrier metal (TiN) can be optimized for high-speed and stable multilevel PRAM.
High-density crossbar arrays based on storage class memory (SCM) are ideally suited to handle an exponential increase in data storage and processing as a central hardware unit in the era of AI-based technologies. To achieve this, selector devices are required to be co-integrated with SCM to address the sneak-path current issue that indispensably arises in such crossbar-type architecture. In this perspective, we first summarize the current state of tellurium-based threshold-switching devices and recent advances in the material, processing, and device aspects. We thoroughly review the physicochemical properties of elemental tellurium (Te) and representative binary tellurides, their tailored deposition techniques, and operating mechanisms when implemented in two-terminal threshold switching devices. Lastly, we discuss the promising research direction of Te-based selectors and possible issues that need to be considered in advance.
As a potential alternative to flash memory, HfO2/Al2O3 stacks appear to be a viable option as charge capture layers in charge trapping memories. The paper undertakes a review of HfO2/Al2O3 stacks as charge trapping layers, with a focus on comparing the number, thickness, and post-deposition heat treatment and γ-ray and white x-ray treatment of such stacks. Compared to a single HfO2 layer, the memory window of the 5-layered stack increased by 152.4% after O2 annealing at ±12 V. The memory window enlarged with the increase in number of layers in the stack and the increase in the Al/Hf content in the stack. Furthermore, our comparison of the treatment of HfO2/Al2O3 stacks with varying annealing temperatures revealed that an increased annealing temperature resulted in a wider storage window. The samples treated with O2 and subjected to various γ radiation intensities displayed superior resistance. and the memory window increased to 12.6 V at ±16 V for 100 kGy radiation intensity compared to the untreated samples. It has also been established that increasing doses of white x-rays induced a greater number of deep defects. The optimization of stacking layers along with post-deposition treatment condition can play significant role in extending the memory window.
This paper demonstrates a novel NAND flash memory structure and annealing configuration including through-silicon via (TSV) inside the silicon substrate to improve annealing efficiency using an electro-thermal annealing (ETA) technique. Compared with the conventional ETA which utilizes WL-to-WL current flow, the proposed annealing method has a higher annealing temperature as well as more uniform heat distribution, because of thermal isolation on the silicon substrate. In addition, it was found that the annealing temperature is related to the electrical and thermal conductivity of the TSV materials. As a result, it is possible to improve the reliability of NAND flash memory. All the results are discussed based on 3-dimensional (3-D) simulations with the aid of the COMSOL simulator.
The electro-thermal erasing (ETE) configuration utilizes Joule heating intentionally generated at word-line (WL). The elevated temperature by heat physically removes stored electrons permanently within a very short time. Though the ETE configuration is a promising next generation NAND flash memory candidate, a consideration of power efficiency and erasing speed with respect to device structure and its scaling has not yet been demonstrated. In this context, based on 3-dimensional (3-D) thermal simulations, this paper discusses the impact of device structure and scaling on ETE efficiency. The results are used to produce guidelines for ETEs that will have lower power consumption and faster speed.
In this paper, we investigated current (I)- and voltage (V)-sweeping properties in a double-stack structure, Ge2Sb2Te5/Ti/W-doped Ge8Sb2Te11, a candidate medium for applications to multilevel phase-change memory. 200-nm-thick Ge2Sb2Te5 and W-doped Ge8Sb2Te11 films were deposited on p-type Si(100) substrate using magnetron sputtering system, and the sheet resistance was measured using 4 point-probe method. The sheet resistance of amorphous-phase W-doped Ge8Sb2Te11 film was about 1 order larger than that of Ge2Sb2Te5 film. The I- and V-sweeping properties were measured using sourcemeter, pulse generator, and digital multimeter. The speed of amorphous-to-multilevel crystallization was evaluated from a graph of resistance vs. pulse duration (t) at a fixed applied voltage (12 V). All the double-stack cells exhibited a two-step phase change process with the multilevel memory states of high-middle-low resistance (HR-MR-LR). In particular, the stable MR state is required to guarantee the reliability of the multilevel phase-change memory. For the Ge2Sb2Te5 (150 nm)/Ti (20 nm)/WGe8Sb2Te11 (50 nm), the phase transformations of HR→MR and MR→LR were observed at t<30ns and t<65ns, respectively. We believe that a high speed and stable multilevel phase-change memory can be optimized by the double-stack structure of proper Ge-Sb-Te films separated by a barrier metal (Ti).
In this study, a TiO2/TiO2-x-based resistance variable memory was fabricated using a DC/RF magnetron sputtering system and ALD. In order to analyze the effect of oxygen plasma treatment on the performance of resistance random access memory (ReRAM), the TiO2/TiO2-x-based ReRAM was evaluated by applying RF power to the TiO2-x oxygen-holding layer at 30, 60, 90, 120, and 150 W, respectively. The ReRAM was fabricated, and the electrical and surface area performances were compared and analyzed. In the case of ReRAM without oxygen plasma treatment, the I-V curve had a hysteresis curve shape, but the width was very small, with a relatively high surface roughness of the oxygen-retaining layer. However, in the case of oxygen plasma treatment, the HRS/LRS ratio for the I-V curve improved as the applied RF power increased; stable improvement was also noted in the surface roughness of the oxygen-retaining layer. It was confirmed that the low voltage drive was not smooth due to charge trapping in the oxygen diffusion barrier layer owing to the high intensity ReRAM applied with an RF power of approximately 150 W.
To enhance the tunneling electroresistance (TER) ratio of a ferroelectric tunnel junction (FTJ) device using Al-doped HfO2 thin films, a thin insulating layer was prepared on a TiN bottom electrode, for which TiN was preliminarily treated at various temperatures in O2 ambient. The composition and thickness of the inserted insulating layer were optimized at 600℃ and 50 Torr, and the FTJ showed a high TER ratio of 430. During the heat treatments, a titanium oxide layer formed on the surface of TiN, that suppressed oxygen vacancy generation in the ferroelectric thin film. It was found that the fabricated FTJ device exhibits two distinct resistance states with higher tunneling currents by properly heat-treating the TiN bottom electrode of the HfO2-based FTJ devices in O2 ambient.
We investigated the rewritable operation of a non-volatile memory device composed of Al (top)/TiO2/ indium-zinc-oxide (IZO)/Al (bottom). The oxygen-deficient IZO layer of the device was spin-coated with 0.1 M indium nitrate hydrate and 0.1 M zinc acetate dehydrate as precursor solutions, and the TiO2 layer was fabricated by atomic layer deposition. The oxygen vacancies IZO layer of an active component annealed at 400℃ using thermal annealing and it was proven to be in oxygen vacancies and oxygen binding environments with OH species and heavy metal ions investigated by X-ray photoelectron spectroscopy. The device, which operates at low voltages (less than 3.5 V), exhibits non-volatile memory behavior consistent with resistive-switching properties and an ON/OFF ratio of approximately 3.6×103 at 2.5 V.
We demonstrate the utilization of ion gel gate dielectrics for operating non-volatile transistor memory devices based on polymer semiconductor thin films. The gating process in typical electrolyte-gated polymer transistors occurs upon the penetration and escape of ionic components into the active channel layer, which dopes and dedopes the polymer film, respectively. Therefore, by controlling doping and dedoping processes, electrical current signals through the polymer film can be memorized and erased over a period of time, which constitutes the transistor-type memory devices. It was found that increasing the thickness of polymer films can enhance the memory performance of device including (i) the current signal ratio between its memorized state and erased state and (ii) the retention time of the signal.
The phase change memory material is an active element in phase change memory and exhibits reversible phase transition behavior by thermal energy input. The doping of the phase change memory material with Ga leads to the increase of its crystallization temperature and the improvement of its amorphous stability. In this study, we investigated the effect of GaGe sputtering power on the formation of the phase change memory material including Ga. The deposition rate linearly increased to a maximum of 127 nm and the surface roughness remained uniform as the GaGe sputtering power increased in the range from 0 to 75 W. The Ga concentration in the thin film material abruptly increased at the critical sputtering power of 60 W. This influence of GaGe sputtering power was confirmed to result from a combined sputtering-evaporation process of Ga occurring due to the low melting point of Ga (29.77℃).
In this study, a substrate-bias assisted 2-step pulse programming method is proposed for realizing 4-bit/1-cell operation of the SONOS memory. The programming voltage and time are considerably reduced by this programming method than a gate-bias assisted 2-step pulse programming method and CHEI method. It is confirmed that the difference of 4-states in the threshold voltage is maintained to more than 0.5 V at least for 10-year for the multi-level characteristics.
For phase transition method, good record sensitivity, low heat radiation, fast crystallization and hi-resolution are essential. Also, a retention time is very important part for phase-transition. In our past papers, we chose composition of Ge1Se1Te2 material to use a Se factor which has good optical sensitivity than conventional Sb. Sb/Ge-Se-Te thin films are fabricated and irradiated with UV light source to investigate a reversible phase change by Sb-doped condition. Because of Sb atoms, the Sb inserted sample showed better performance than conventional one. We should note that this novel one showed another possibility for phase-change random access memory.
In this study, Ge8Se(2+x)Te(6-x) thin film amorphous-to-crystalline phase-change rate was evaluated in using a nano-pulse scanner. The focused laser beam with a diameter <10 μm was illuminated in the power (P) and pulse duration (t) ranges of 1-31 mW and 10-460 ns, respectively, with subsequent detection of the responsive signals reflected from the film surface. We also evaluated the material characteristics, such as optical absorption and energy gap, crystalline phases, and sheet resistance of as-deposited and annealed films. The result of experiments showed that the thermal stability of the Ge-Se-Te film is largely improved by adding Se.
In this paper, in order to suppress unwanted current paths originating from adjacent cells in a passive crossbar array based on resistive random access memory (RRAM) without extrinsic switching devices, 1-diode type RRAM which consists of a 0.2% chromium-doped strontium titanate (Cr-SrTiO3) film deposited on a silicon substrate, was proposed for high packing density, and intrinsic rectifying characteristics from the current versus voltage characteristics were successfully demonstrated.
The charged particle type display is a kind of the reflectivity type display and shows an image by absorption and reflection of external light source, which has keep an image without additional electric power because of bistability. In this paper, we made a device whose cell gap is 56 ㎛ and also analyzed driving and memory characteristics by applied driving voltages. As a result, we found that the driving voltage and memory effect depend on q/m(charge to mass ratio) of charged particle. In this case of breakdown voltage, the devices showed degradation of reflectivity and memory effect due to irregular movement of overcharged particles. In addition, contrast ratio of the device varies with memory effect. Thus, we consider that device needs uniform q/m for improvement of electric and optical properties and memory effect.
An amorphous Ge2Sb2Te5 thin film is one of the most commonly used materials for phase-change data storage. In this study, Aux(Ge2Sb2Te5)1-x thin film amorphous-to-crystalline phase-change rate were evaluated in using 658 nm laser beam. The focused laser beam with a diameter <10 μm was illuminated in the power (P) and pulse duration (t) ranges of 1-17 mW and 10-460 ns, respectively, with subsequent detection of the responsive signals reflected from the film surface. We also evaluated the material characteristics, such as optical absorption and energy gap, crystalline phases, and sheet resistance of as-deposited and annealed films. The result of experiments showed that the thermal stability of the Ge2Sb2Te5 film is largely improved by adding Au.
In this paper, Fin-type silicon-oxide-nitride-oxide-silicon (SONOS) flash memory are fabricated and the electrical characteristics are analyzed. Compared to the planar-type SONOS devices, Fin-type SONOS devices show good short channel effect (SCE) immunity due to the enhanced gate controllability. In memory characteristics such as program/erase speed, endurance and data retention, Fin-type SONOS flash memory are also superior to those of conventional planar-type. In addition, Fin-type SONOS device shows improved SCE immunity in accordance with the decrease of Fin width. This is known to be due to the fully depleted mode operation as the Fin width decreases. In Fin-type, however, the memory characteristic improvement is not shown in narrower Fin width. This is thought to be caused by the Fin structure where the electric field of Fin top can interference with the Fin side electric field and be lowered.
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