This study investigates the effect of dielectric layer thickness on the electrical and reliability characteristics of BaTiO₃- based X8R multilayer ceramic capacitors (MLCCs) for automotive applications. MLCCs with 30 dielectric layers and thicknesses ranging from 5 to 30 μm were fabricated, and key parameters―including capacitance, equivalent series resistance (ESR), insulation resistance (IR), breakdown voltage (BDV), DC-bias characteristics, temperature coefficient of capacitance (TCC), and ripple current-induced heating―were evaluated. The dielectric constant (~2,000) and sintering shrinkage (~-25%) were nearly independent of thickness, confirming stable microstructure formation. ESR increased with thickness, while normalized BDV (V/μm) decreased due to defect accumulation. IR improved with increasing thickness but dropped sharply above 125℃. Dielectrics thinner than 10 μm exhibited significant capacitance degradation under DC-bias and temperature variation, reflecting strong internal field effects. Ripple-induced heating correlated directly with ESR. These results indicate that, although thinner layers enhance capacitance density, reducing the thickness below 10 μm compromises bias stability and thermal reliability. A minimum dielectric thickness of 10 μm is therefore recommended to achieve an optimal balance between electrical performance and durability in high-reliability X8R MLCCs.

The increasing global demand for renewable energy has accelerated the deployment of offshore wind farms, thereby highlighting the need for advanced development and performance assessment techniques for dynamic submarine cables used in floating offshore wind systems. These cables are continuously subjected to combined thermal, electrical, and mechanical stresses, with mechanical loading playing a particularly dominant role. As a result, dynamic submarine cables exhibit degradation behaviors that differ significantly from those of conventional fixed submarine cables. This paper presents the design and implementation of a comprehensive evaluation system capable of applying combined thermal, electrical, and mechanical stresses to dynamic submarine cables. The system was validated using a 66 kV wet type submarine cable through commissioning tests and insulation performance measurements. Electrical stress of 72 kV, thermal stress exceeding 95°C, and mechanical stress corresponding to a bending radius of 20 times the cable diameter over 20 cycles were applied to verify system reliability. The subsequent insulation assessments quantitatively confirmed performance variations induced by the combined stresses. The results demonstrate that the proposed platform is the first system capable of simultaneously applying thermal, electrical, and mechanical stresses to dynamic submarine cables, and its operational performance has been successfully validated. This platform enables realistic reliability evaluation of dynamic cables used in floating offshore wind farms and is expected to improve the overall operational reliability of offshore wind power systems.

The rapid proliferation of artificial intelligence (AI) servers and high-performance computing systems has significantly elevated the technical and reliability requirements for multilayer ceramic capacitors (MLCCs). In such systems, MLCCs are critical passive components that must deliver high capacitance, fast transient response, and robust insulation performance under high temperature, voltage, and current density. This review examines the material, structural, and process innovations that underpin MLCC performance in AI applications. Key topics include the development of ultrathin dielectric layers (<0.5 μm), rare-earth doped BaTiO₃-based dielectrics with enhanced DC bias stability, and core-shell microstructures designed for temperature and field resilience. The paper also explores insulation degradation mechanisms―such as vacancydriven conduction and demixing―and advanced reliability assessment methodologies, including HALT, TSDC, and the tipping point framework. Comparisons with automotive-grade MLCCs highlight the unique requirements of AI systems, such as ultraminiaturization, high volumetric efficiency, and ppm-level field failure rates. Finally, the review discusses emerging trends in MLCC technology, including particle engineering, interface stabilization, and advanced lamination techniques, and provides insight into the future direction of capacitor development tailored to AI data center environments.

To ensure the long-term reliability of flexible photovoltaic (FPV) modules, it is crucial to develop an effective moisture barrier layer that prevents the infiltration of moisture and oxygen. We developed such a layer composed of parylene (700 nm) and AlOx (70 nm), optimizing its material properties, moisture-blocking performance, and processing conditions. The barrier layer applied to the Ethylene Tetrafluoroethylene (ETFE) substrate demonstrated a water vapor transmission rate (WVTR) of 6.33 × 10^-2 g/m²/day and an average visible light transmittance (AVT) of 85.3% over the 380-780 nm wavelength range. For the FPV module with this barrier, Damp/Heat (DH) reliability testing was conducted at 85℃ and 85% relative humidity for up to 1,000 hours. During testing, the power conversion efficiency (PCE) decreased slightly from 25.4% (0 hr) to 24.7% (1,000 hr), reflecting a minimal reduction of only 0.7%. The primary cause of degradation was identified as a -4% relative change in shortcircuit current density (JSC) before and after DH testing. Consequently, the ETFE/parylene/AlOx multilayer moisture barrier proved highly effective in ensuring the long-term reliability of solar modules.

Aggressive device scaling has severely degraded the switching characteristics of CMOS transistors. This issue has led to the development of tunneling FETs (TFETs) as an alternative. TFETs, with their asymmetric doping of the source and drain regions, offer improved subthreshold swing (SS) compared to conventional MOSFETs. However, despite this advantage, TFETs still suffer from ambipolar current, which increases off-state current (IOFF). This paper introduces an approach to applying hetero gate dielectrics (HGDs) in nanosheet (NS) TFETs to reduce ambipolar current characteristics. The magnitude of the drain electric field is reduced by selectively forming a high-k dielectric near the source region This configuration allows the TFETs to avoid unintended band-to-band tunneling (BTBT) and suppress ambipolar current during the off-state.

Post-metallization annealing (PMA) has been employed in silicon-based CMOS fabrication to enhance MOSFET reliability and performance. However, although deuterium annealing can reduce interface traps between the Si and SiO₂ gate dielectric, it remains insufficient to fully passivate these traps. In this context, a multiple PMA process, including additional hydrogen annealing, is proposed to further reduce dangling bonds. Silicon-based MOSFETs are fabricated to verify the proposed annealing process architecture. Electrical characterization of the threshold voltage (VTH), subthreshold swing (SS), on-state current (ION), and carrier mobility (μ_n) is conducted to investigate the impact of the multiple PMA. This study provides a guideline for PMA in MOSFET fabrication, with improvements in both performance and reliability.

Recently, as environmental issues caused by gas stoves have led to the widespread adoption of induction appliances, specialized cookware for induction is essential. However, due to the inability of ceramic containers to be directly used on induction cooktops, a conductive coating is required on the bottom of the cookware, presenting limitations such as complex deposition processes and extended coating times in existing methods including thermal spraying, dip coating, and transcription method. We confirmed the potential of heat-resistant cookware for induction use by coating the bottom of the ceramic container with Ag through a simple manufacturing process of screen-printing and measuring its thermal conductivity and reliability. The Ag-coated ceramic cookware produced by screen-printing demonstrated similar thermal conductivity and reliability to those made using the traditional method of transfer printing. In addition, the adhesive strength before and after thermal shock testing was even superior in the screen-printing method, which suggests a higher expected lifespan. As a result, it is expected that induction-compatible heat-resistant ceramic containers with excellent performance and lifespan will be manufactured through the screen-printing process, which is more cost-effective and efficient compared to other methods.

Various process modifications have been used to minimize SiO₂ gate oxide aging in metal-oxide-semiconductor field-effect transistors (MOSFETs). In particular, post-metallization annealing (PMA) with a deuterium ambient can effectively eliminate both bulk traps and interface traps in the gate oxide. However, even with the use of PMA, it remains difficult to prevent high levels of radiation-induced gate oxide damage such as total ionizing dose (TID) during long-term missions. In this context, additional low-temperature heat treatment (LTHT) is proposed to recover from radiation-induced damage. Positive traps in the damaged gate oxide can be neutralized using LTHT, thereby prolonging device reliability in harsh radioactive environments.

This paper demonstrates a novel NAND flash memory structure and annealing configuration including through-silicon via (TSV) inside the silicon substrate to improve annealing efficiency using an electro-thermal annealing (ETA) technique. Compared with the conventional ETA which utilizes WL-to-WL current flow, the proposed annealing method has a higher annealing temperature as well as more uniform heat distribution, because of thermal isolation on the silicon substrate. In addition, it was found that the annealing temperature is related to the electrical and thermal conductivity of the TSV materials. As a result, it is possible to improve the reliability of NAND flash memory. All the results are discussed based on 3-dimensional (3-D) simulations with the aid of the COMSOL simulator.

The electro-thermal erasing (ETE) configuration utilizes Joule heating intentionally generated at word-line (WL). The elevated temperature by heat physically removes stored electrons permanently within a very short time. Though the ETE configuration is a promising next generation NAND flash memory candidate, a consideration of power efficiency and erasing speed with respect to device structure and its scaling has not yet been demonstrated. In this context, based on 3-dimensional (3-D) thermal simulations, this paper discusses the impact of device structure and scaling on ETE efficiency. The results are used to produce guidelines for ETEs that will have lower power consumption and faster speed.

High pressure deuterium (HPD) annealing is an advancing technology for the fabrication of modern semiconductor devices. In this work, gate-enclosed FETs are fabricated on a silicon substrate as test vehicles. After a cycle for the HPD annealing, the device parameters such as threshold voltage (V_TH), subthreshold swing (SS), on-state current (I_ON), off-state current (I_OFF), and gate leakage (I_G) were measured and compared depending on the HPD. The HPD annealing can passivate the dangling bonds at Si-SiO₂ interfaces as well as eliminate the bulk trap in SiO₂. It can be concluded that adding the HPD annealing as a fabrication process is very effective in improving device reliability, performance, and variability.

Localized heat can be generated using electrically conductive word-lines built into a 3D NAND flash memory string. The heat anneals the gate dielectric layer and improves the endurance and retention characteristics of memory cells. However, even though the electro-thermal annealing can improve the memory operation, studies to investigate material failures resulting from electro-thermal stress have not been reported yet. In this context, this paper investigated how applying electro-thermal annealing of 3D NAND affected mechanical stability. Hot-spots, which are expected to be mechanically damaged during the electro-thermal annealing, can be determined based on understanding material characteristics such as thermal expansion, thermal conductivity, and electrical conductivity. Finally, several guidelines for improving mechanical stability are provided in terms of bias configuration as well as alternative materials.

Reliability of CMOS has been severed under aggressive device scaling. Conventional technologies such as lightly doped drain (LDD) and forming gas annealing (FGA) have been applied for better device reliability, but further advances are modest. Alternatively, electro-thermal annealing (ETA) which utilizes Joule heat produced by electrodes in a MOSFET, has been newly introduced for gate dielectric curing. However, concerns about mechanical stability during the electro-thermal annealing, have not been discussed, yet. In this context, this paper demonstrates the mechanical stability of nanosheet FET during the electro-thermal annealing. The effect of mechanical stresses during the electro-thermal annealing was investigated with respect to device design parameters.

In this study, solder joints mixed with graphene-nanosheets (GNSs) were investigated for the manufacture of highly reliable electronic devices. In order to analyze the effect of adding GNSs, experiments were performed by adding various amounts of GNSs (0.01, 0.05, 0.1, 0.3, 0.5 wt%). To compare and analyze the properties of the solder joints to which GNSs were added, shear forces were measured, and cross-sectional observation was performed. The bonding strength of the solder joints containing 0.05% GNSs was the highest, and the bonding strength of the solder joints with higher GNSs contents did not increase. This is because, as the content of GNSs increases, the viscosity of the solder paste also increases; therefore, the solder paste detachability from the metal mask was lowered and a sufficient amount was not applied. In addition, due to the high content of GNSs, the fluidity of solder powder and paste decreased, resulting in defects in the shape of the solder joint. Therefore, the optimal GNSs content in this study was 0.05%, and studies for optimal viscosity should be continued.

High reliability thin film transistors are important factors for next-generation displays. The reliability of transparent a-IGZO semiconductors is being actively studied for display applications. A plasma treatment can fill the oxygen vacancies in the channel layer and the channel layer/insulating layer interface so that the device can work stably under a bias voltage. This paper studies the effect of plasma treatment on the performance of a-IGZO TFT devices. The influence of different plasma gases on the electrical parameters of device and its working reliability are reviewed. The article mentions argon, fluorine, hydrogen and several ways of processing in the atmosphere. Among these methods, F (fluorine) plasma treatment can maximize equipment reliability. It is expected that the presented results will form a basis for further research to improve the reliability of a-IGZO TFT.

In this report, the results of a systematic study on the effects of polycrystalline silicon gate depletion on the reliability characteristics of metal-oxide semiconductor field-effect transistor (MOSFET) devices were discussed. The devices were fabricated using standard complimentary metal-oxide semiconductor (CMOS) processes, wherein phosphorus ion implantation with implant doses varying from 10¹³ to 5×10¹⁵ cm^-2 was performed to dope the polycrystalline silicon gate layer. For implant doses of 10¹⁴/㎠ or less, the threshold voltage was increased with the formation of a depletion layer in the polycrystalline silicon gate layer. The gate-depletion effect was more pronounced for shorter channel lengths, like the narrow-width effect, which indicated that the gate-depletion effect could be used to solve the short-channel effect. In addition, the hot-carrier effects were significantly reduced for implant doses of 10¹⁴/㎠ or less, which was attributed to the decreased gate current under the gate-depletion effects.

Insulators used in overhead transmission lines are continuously exposed to a number of mechanical and electrical stresses owing to external environmental factors, resulting in corrosion, reduction in durability, and deterioration. Widely used porcelain insulators are fabricated with cement and porcelain and are especially common in Korea. Changes in the hardness and chemical reactivity of the cement increase the leakage and fault currents and increase the possibility of flashover due to insulation breakdown. Therefore, it is important to evaluate the durability and defects of porcelain insulators. Studies on the reliability of various evaluation methods are needed to prevent accidents by accurately determining the replacement timing and potential defects in porcelain insulators. In this study, the hardness of the cement part of the porcelain insulator was measured using the Vickers hardness test and its composition was analyzed by energy dispersive spectroscopy and X-ray diffraction analysis. The performance of the insulators was compared in two different regions with varying climatic conditions. This study presents an evaluation method of the defects in porcelain insulators by measuring humidity, which can also be used to assess the reliability of the insulators.

Using both EVA and POE encapsulants, we fabricated polycrystalline Si PV modules and performed a set of reliability tests of PID, DH, TC, and Complex prior to outdoor installation. The power output with temperatures and insolation as well as I-V characteristics had been monitored under outdoor environments for 18 months. In the entire period, the total power of 3,576 kWh from POE PV modules was observed larger than 3,449 kWh from EVA PV modules by 3.5%. All the PV modules showed a 5.6~9.2% drop in the conversion efficiency. As for the solar power generation, the PV modules performed through PID, TC test revealed distinct difference in between EVA and POE for which the POE PV module produced more power by +11.4% and +6.6%, respectively, as measured in the 18^th month. In addition, POE was proved to protect better the solar cells under PID influence.

It is summarized that potential causes of performance degradations and failure mechanisms ofcrystalline silicon photovoltaic (PV) modules installed in Middle East area. In addition, we also reviewedcurrent PV module qualification test (IEC 61215) and the methods for detection of wear-out fault. Thefailure of PV modules in the extreme environmental conditions such as deserts is mainly due to hightemperature, humidity, and dust storms. In particular, cementation phenomenon caused by combination ofsand and moisture leads to rapid degradation in the performance of PV modules. In order to evaluate andguarantee the long term reliability of PV modules, specific qualification tests such as sand dust test, saltmist test and potential induce degradation test considering operating environment of PV module should becarried out.

Encapsulant curing in terms of convection oven leads to thermal induced stress due to nonuniform thermal conductivity in LED package. We have adopted infrared (IR) light for silicone curing in order to release the stress. The light uniformity irradiated on an encapsulant surface is confirmed to be uniform by optical simulation. Shear strength of die paste using IR compared to convection oven is increased 19.2% at the same curing time, which indicates curing time can be shortened. The indentation depth difference between center and edge of silicone encapsulant in terms of convection oven and IR are 14.8% and 3.4%, respectively. Curing by IR also shows 2.3% better radiant flux persistency rate of LED at 85℃ after 1,000 h reliability test compared to convection curing.

In this study, the characteristics and error ranges of the mechanical bonding strength were analyzed according to before and after thermal shock test for various chips of automotive application component using Sn-3.0Ag-0.5Cu solder. In the after thermal shock test, the mechanical bonding strengths tend to decrease, meanwhile decreasing rates of mechanical strengths were less then 12% at specimen`s bonding area below 3.5mm2, and were from 17 to 21% at specimen`s bonding area above 12 mm2. On the other hand, Specimen`s mean deviation rates were about 5% at specimen`s bonding area more than 12 mm2. Inversely, at specimen`s bonding area is less then 3.5 mm2, mean deviation rates were increased to about 8%. It means that the smaller device size is, the larger mean deviation rate. In addition, error ranges and deviation rates of the mechanical bonding strengths may differ slightly depending on their bonding area. Furthermore, process conditions as well as method of mechanical reliability evaluation should be established to reduce the error ranges of bonding strength.

This paper presents the design and reliability evaluation of metallized film capacitor for power electronics application. The rated voltage of development capacitor is DC 3300[V], the capacitance is 5 μF and the ripple current capability is 130 A(rms). Film metallization and patterns are an important design factor that has been development enhance the electric and reliability properties of film capacitor for power electro nics. In term of capacitor construction and metallized pattern is one of the parameters that can be modified to further improve the rating in the terms of maximum ripple current and lifetime. This capacitor can be used as snubber capacitor application such as power train invertor system.