The ability to manipulate and probe biomolecules at the single-molecule level has become an essential approach for understanding molecular interactions, conformational dynamics, and nanoscale transport phenomena. Advances in experimental techniques have enabled precise control of individual molecules with high spatial resolution and piconewton-level force sensitivity. These developments have significantly expanded the capability of studying biomolecular mechanics and dynamics beyond conventional ensemble measurements. A variety of physical strategies have been developed for single-molecule manipulation, including mechanical-force-based approaches, electric-field-driven methods, and nanoscale structural confinement techniques. Mechanical-force-based methods, such as optical tweezers, magnetic tweezers, and atomic force microscopy, enable direct measurement of molecular mechanical responses. Electric-field-based manipulation, represented by dielectrophoresis, allows noncontact control of particles and biomolecules through polarization effects in non-uniform electric fields. In addition, nanopore-based systems employ nanoscale confinement to regulate molecular transport and residence behavior. This review provides an overview of representative single-molecule manipulation techniques based on mechanical, electrical, and structural control and discusses their fundamental principles and implementation strategies.
This work focuses on improving the light-harvesting efficiency of thin-film silicon solar cells through innovative multi-architecture surface modifications. To create a regular optical structure, a lithographic process was performed to form it on a glass substrate through various etching processes, from Etch-1 to Etch-3. AZO was deposited on top of the structures and re-etched to create a multi-architectural surface. These surface-modified structures improved the light absorption and overall performance of the solar cell through changes in optical and physical properties, which we will analyze. In addition, we investigated the effect of post-cleaning on the etched glass structures through EDX analysis to understand the mechanism of the etching action. The results of this study are expected to provide important guidelines for the design and fabrication of solar cells and other photovoltaic devices.
As a potential alternative to flash memory, HfO2/Al2O3 stacks appear to be a viable option as charge capture layers in charge trapping memories. The paper undertakes a review of HfO2/Al2O3 stacks as charge trapping layers, with a focus on comparing the number, thickness, and post-deposition heat treatment and γ-ray and white x-ray treatment of such stacks. Compared to a single HfO2 layer, the memory window of the 5-layered stack increased by 152.4% after O2 annealing at ±12 V. The memory window enlarged with the increase in number of layers in the stack and the increase in the Al/Hf content in the stack. Furthermore, our comparison of the treatment of HfO2/Al2O3 stacks with varying annealing temperatures revealed that an increased annealing temperature resulted in a wider storage window. The samples treated with O2 and subjected to various γ radiation intensities displayed superior resistance. and the memory window increased to 12.6 V at ±16 V for 100 kGy radiation intensity compared to the untreated samples. It has also been established that increasing doses of white x-rays induced a greater number of deep defects. The optimization of stacking layers along with post-deposition treatment condition can play significant role in extending the memory window.
The piezoelectric energy harvesting characteristics of a trapezoidal cantilever generator with lead zirconate titanate (PZT) laminate were investigated with various Ag inner electrodes. The piezoelectric mode of operation was a transverse mode by using a planar electrode pattern. The piezoelectric cantilever generator was fabricated using trapezoidal cofired-PZT/Ag laminates by five specimens of 2, 3, 4, 7, and 13 layers of Ag. As the number of Ag electrodes increased, impedance and output voltage at resonant frequency significantly decreased, and capacitance and output current showed an increasing tendency. A maximum output power density of 7.60 mW/cm3 was realized for the specimen with seven Ag layers in the optimal condition of acceleration (1.2 g) and resistive load (600 Ω), which corresponds to a normalized power factor of 5.28 mW/g2·cm3.
The effects of off-state bias stress on the characteristics of p-type poly-Si TFT were investigated. To reduce the gate-induced drain leakage (GIDL) current, the off-state bias stress was changed by varying Vgs and Vds. After application of the off-state bias stress, the Vgs causing GIDL current was dramatically increased from 1 to 10 V, and thus, the Vgs margin to turn off the TFT was improved. The on-current and subthreshold swing in the aged TFT was maintained. We performed a technology computer-aided design (TCAD) simulation to describe the aged characteristics. The aged-transfer characteristics were well described by the local charge trapping. The activation energy of the GIDL current was measured for the pristine and aged characteristics. The reduced GIDL current was mainly a thermionic field-emission current.
In this work, we investigate the effects of lithium doping on the electric performance of solution-processed n-type zinc tin oxide (ZTO)/p-type silicon carbide (SiC) heterojunction diode structures. The proper amount of lithium doping not only affects the carrier concentration and interface quality but also influences the temperature sensitivity of the series resistance and activation energy. We confirmed that the device characteristics vary with lithium doping at concentrations of 0, 10, and 20 wt%. In particular, the highest rectification ratio of 1.89×107 and the lowest trap density of 4.829×1,022 cm-2 were observed at 20 wt% of lithium doping. Devices at this doping level showed the best characteristics. As the temperature was increased, the series resistance value decreased. Additionally, the activation energy was observed to change with respect to the component acting on the trap. We have demonstrated that lithium doping is an effective way to obtain a higher performance ZTO-based diode.
In this study, we compared the threshold-voltage extraction methods of accumulation-type JLDG (junctionless double-gate) MOSFETs (metal-oxide semiconductor field-effect transistors). Threshold voltage is the most basic element of transistor design; therefore, accurate threshold-voltage extraction is the most important factor in integrated-circuit design. For this purpose, analytical potential distributions were obtained and diffusion-drift current equations for these potential distributions were used. There are the ømin method, based on the physical concept; the linear extrapolation method; and the second and third derivative method from the Id-Vg relation. We observed that the threshold-voltages extracted using the maximum value of TD (third derivatives) and the ømin method were the most reasonable in JLDG MOSFETs. In the case of 20 nm channel length or more, similar results were obtained for other methods, except for the linear extrapolation method. However, when the channel length is below 20 nm, only the ømin method and the TD method reflected the short-channel effect.
We fabricated 1-D and 2-D diffraction gratings of SiOx anti-reflection (AR) film grown on a quartz substrate and integrated them into a c-Si photovoltaic (PV) submodule. The light-trapping effect of the resulting submodules was studied in terms of the oblique optical incident angle, θi. As the θi increased, solar conversion efficiency, η, was improved as expected by the increased optical transmission caused by the grating. For θi≤30°, the relative solar conversion efficiency, Δη, of a 1-D SiOx (t=300 nm) grating, compared to that of a flat SiOx AR-coated integrated PV submodule, was improved very little, with a small variation of within 2%, but increased markedly for θi≥40°. We observed a change of Δη as large as 10.7% and 9.5% for the SiOx grating of period t=800 nm and 1200 nm, respectively. For a 2-D SiOx (t=300 nm) grating integrated PV submodule, however, the optical trapping behavior was similar in terms of θi but its variation was small, within ±1.0%.
In this study, we observed current-voltage characteristics of the MIM (metal-insulator-metal) structure. The WOx material was used between metal electrodes as the oxide insulator. The structure of the Al/WOx/TiN shows bipolar resistive switching and the operating direction of the resistive switching is clockwise, which means set at negative voltage and reset at positive voltage. The set process from HRS (high resistance state) to LRS (low resistance state) occurred at - 2.6 V . The reset process from LRS to HRS occurred at 2.78 V . The on/off current ratio was about 10 and resistive switching was performed for 5 cycles in the endurance characteristics. With consecutive switching cycles, the stable Vset and Vreset were observed. The electrical transport mechanism of the device was based on the migration of oxygen ions and the current-voltage curve is following (Ohm``s Law → Trap-Controlled Space Charge Limited Current → Ohm``s Law) process in the positive voltage region.
In this paper, we investigated the hot carrier reliability of two kinds of device with low threshold voltage (LVT) and regular threshold voltage (RVT) in 65 nm CMOS technology. Contrary to the previous report that devices beyond 0.18 μm CMOS technology is dominated by channel hot carrier(CHC) stress rather than drain avalanche hot carrier(DAHC) stress, both of LVT and RVT devices showed that their degradation is dominated by DAHC stress. It is also shown that in case of LVT devices, contribution of interface trap generation to the device degradation is greater under DAHC stress than CHC stress, while there is little difference for RVT devices.
We have investigated the effect of electrical properties of amorphous InGaZnO thin filmtransistors (a-IGZO TFTs) by post thermal annealing in O2 ambient.The post-annealed in O2 ambienta-IGZOTFT is found to be more stable to be used for oxide-based TFT devices, and has betterperformance, such as the on/off current ratios, sub-threshold voltage gate swing, and, as well asreasonable threshold voltage, than others do. The interface trap density is controlled to achieve theoptimum value of TFT transfer and output characteristics. The device performance is significantlyaffected by adjusting the annealing condition. This effect is closely related with the modulation annealingmethod by reducing the localized trapping carriers and defect centers at the interface or in the channellayer.
The effect of oxygen pressure in the synthesis of ZnO nanostructures through thermal evaporation of Zn powder was investigated. The thermal evaporation process was carried out in oxygen ambient for 1 hr at 1,000℃ under different pressures. The oxygen pressure was changed in range of 0.5 ? 900 Torr. Any nanostructure was not formed on the specimens prepared at oxygen pressures lower than 10 Torr. When oxygen pressure was 100 Torr, ZnO nanowires were observed. With increasing the oxygen pressure to 500 Torr, the morphology of ZnO nanostructures changed from wire to tetrapod. For all the samples, room temperature photoluminescence spectra show a strong green emission peak at around 550 nm.
We report on variations of electrical properties with different active layer thickness and post-annealing temperature in amorphous In-Ga-Zn-O (IGZO) thin-film transistors (TFTs). In particular, subthreshold swing (SS) of the IGZO-TFTs was improved as increasing the active layer thickness at an given post-annealing temperature, accompanying the negative shift in turn-off voltage. However, as increasing post-annealing temperature, only turn-off voltage was shifted negatively with almost constant SS value. The effect of the active layer thickness and post-annealing temperature on electrical properties, such as SS, field effect mobility and turn-off voltage in IGZO-TFTs has been explained in terms of the variation of trap density in IGZO channel layer and at gate dielectric/IGZO interface.
In this paper, reliability of the two sandwiched MIM capacitors of Al2O3-HfO2-Al2O3 (AHA) and SiO2-HfO2-SiO2 (SHS) with hafnium-based dielectrics was analyzed using two kinds of voltage stress; DC and AC voltage stresses. Two MIM capacitors have high capacitance density (8.1 fF/μm2 and 5.2 fF/μm2) over the entire frequency range and low leakage current density of ∼1 nA/cm2 at room temperature and 1 V. The charge trapping in the dielectric shows that the relative variation of capacitance (ΔC/C0) increases and the variation of voltage linearity (α/α0) gradually decreases with stress-time under two types of voltage stress. It is also shown that DC voltage stress induced greater variation of capacitance density and voltage linearity than AC voltage stress.
In this paper, flicker noise characteristic and channel hot carrier degradation of NMOSFETs with plasma nitrided oixde (PNO) and thermally nitrided oxide (TNO) are analyzed in depth. Compared with NMOSFET with TNO, flicker noise characteristic of NMOSFET with PNO is improved significantly because nitrogen density in PNO near the Si/SiO2 interface is less than that in TNO. However, device degradation of NMOSFET with PNO by channel hot carrier stress is greater than that with TNO although PMOSFET with PNO showed greater immunity to NBTI degradation than that with TNO in previous study. Therefore, concurrent investigation of the reliability as well as low frequency noise characteristics of NMOSFET and PMOSFET is required for the development of high performance analog MOSFET technology.
In this paper, we investigated an anomalous hump phenomenon under the positive bias stress in p-type LTPS TFTs. The devices with inferior electrical performance also show larger hump phenomenon. which can be explained by the sub-channel induced from trapped electrons under thinner gate oxide region. We can confirm that the devices with larger hump have larger interface trap density (Dit) and grain boundary trap density (Ntrap) extracted by low-high frequency capacitance method and Levinson-Proano method, respectively. From the C-V with I-V transfer characteristics, the trapped electrons causing hump seem to be generated particularly from the S/D and gate overlapped region. Based on these analysis, the major cause of an anomalous hump phenomenon under the positive bias stress in p-type poly-Si TFTs is explained by the GIDL occurring in the S/D and gate overlapped region and the traps existing in the channel edge region where the gate oxide becomes thinner, which can be inferred by the fact that the magnitude of the hump is dependent on the average trap densities.
Recently, amorphous oxide semiconductors (AOSs) based thin-film transistors (TFTs) have received considerable attention for application in the next generation displays industry. The research trends of AOSs based TFTs investigation have focused on the high device performance. The electrical properties of the TFTs are influenced by trap density. In particular, the threshold voltage (Vth) and subthreshold swing (SS) essentially depend on the semiconductor/gate-insulator interface trap. In this article, we investigated the effects of Ar plasma-treated SiO2 insulator on the interfacial property and the device performances of amorphous indium gallium zinc oxide (a-IGZO) TFTs. We report on the improvement in interfacial characteristics between a-IGZO channel layer and gate insulator depending on Ar power in plasma process, since the change of treatment power could result in different plasma damage on the interface.
Poly Si TFTs (poly silicon thin film transistors) with p channel those are annealed HT (high t emperature) with gate poly crystalline silicon and LT (low temperature) with metal gate electrode were fabricated on quartz substrate using the analyzed data and compared according to the activated grade silicon thin films and the size of device channel. The electrical characteristics of HT poly-Si TFTs increased those are the on current, electron mobility and decrease threshold voltage by the quality of particles of active thin films annealed at high temperature. But the on/off current ratio reduced by increase of the off current depend on the hot carrier applied to high gate voltage. Even though the size of the particles annealed at low temperature are bigger than HT poly-Si TFTs due to defect in the activated grade poly crystal silicon and the grain boundary, the characteristics of LT poly-Si TFTs were investigated deterioration phenomena those are decrease the electric off current, electron mobility and increase threshold voltage. The results of transconductance show that slope depend on the quality of particles and the amplitude depend on the size of the active silicon particles.
ZnO nanostructures with tetrapod, needle and multipod shapes were synthesized without catalysts through a simple thermal oxidation of metallic Zn powder in alumina crucible under air atmosphere. X-ray diffraction data revealed that the ZnO nanostructures had wurtzite structure of hexagonal phase. Energy dispersive X-ray (EDX) spectra showed that the ZnO was of high purity. After the oxidation of Zn powder, white colored product was mainly observed and yellow colored product was observed only a very little on the surface of the oxidized source materials. The white product consisted of tetrapods, while yellow product was composed of needles and multipods. Cathodoluminescece spectra showed that the crystalline quality of tetrapods was better that those of needles and multipods.
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