The rapid proliferation of artificial intelligence (AI) servers and high-performance computing systems has significantly elevated the technical and reliability requirements for multilayer ceramic capacitors (MLCCs). In such systems, MLCCs are critical passive components that must deliver high capacitance, fast transient response, and robust insulation performance under high temperature, voltage, and current density. This review examines the material, structural, and process innovations that underpin MLCC performance in AI applications. Key topics include the development of ultrathin dielectric layers (<0.5 μm), rare-earth doped BaTiO₃-based dielectrics with enhanced DC bias stability, and core-shell microstructures designed for temperature and field resilience. The paper also explores insulation degradation mechanisms―such as vacancydriven conduction and demixing―and advanced reliability assessment methodologies, including HALT, TSDC, and the tipping point framework. Comparisons with automotive-grade MLCCs highlight the unique requirements of AI systems, such as ultraminiaturization, high volumetric efficiency, and ppm-level field failure rates. Finally, the review discusses emerging trends in MLCC technology, including particle engineering, interface stabilization, and advanced lamination techniques, and provides insight into the future direction of capacitor development tailored to AI data center environments.
Next-generation wide-bandgap semiconductors such as SiC, GaN, and Ga2O3 are being considered as potential replacements for current silicon-based power devices due to their high mobility, larger size, and production of high-quality wafers at a moderate cost. In this study, we investigate the gradual modulation of chemical composition in multi-stacked metal oxide semiconductor thin films to enhance the performance and bias stability of thin-film transistors (TFTs). It demonstrates that adjusting the Ga ratio in the indium gallium oxide (IGO) semiconductor allows for precise control over the threshold voltage and enhances device stability. Moreover, employing multiple deposition techniques addresses the inherent limitations of solution-processed amorphous oxide semiconductor TFTs by mitigating porosity induced by solvent evaporation. It is anticipated that solution-processed indium gallium oxide (IGO) semiconductors, with a Ga ratio exceeding 50%, can be utilized in the production of oxide semiconductors with wide band gaps. These materials hold promise for power electronic applications necessitating high voltage and current capabilities.
Magnetoelectric (ME) properties of 3-0 type particulate composites have been investigated with respect to application features for reliable magnetic sensitivity and magnetically-induced output voltage. In order to figure out the magnetoelectric characteristics in the ME composites, frequency dependent ME responses were studied from [0.948 Na0.5K0.5NbO3-0.052 LiSbO3]-[Co1-xZnxFe2O4] (NKNLS)/Co1-xZnxFe2O4 (CZFO, x=0, 0.1, and 0.2). As a result, the maximal αME of 23.15 mV/cm·Oe was achieved from the NKNLS-CZFO (xZn = 0.1) composites at resonance frequency of 315 kHz and Hdc = 0 Oe. From the frequency dependent ME responses, it is clearly described that the self-biased ME composites can be used for applications as both magnetic sensors and energy harvesters, respectively.
Electrical poling is a crucial step to convert ferroelectrics to piezoelectrics. Nevertheless, no systematic investigation on the effect of poling has been reported. Given that the poling involves an alignment of spontaneous polarization, the condition for poling should be different when a material has an internal bias field that influences the domain stability. Here, we present the effect of poling profile on the dielectric and piezoelectric properties in Mn-doped Pb(Mg1/3Nb2/3)O3-29 mol%PbTiO3 single crystal with an internal bias field. We showed that both the dielectric permittivity and the piezoelectric coefficient were further enhanced when the poling procedure ends with a field application along the opposite direction to the internal bias field. We expect that the current finding would give a clue to understanding the true mechanism for the electrical poling.
The transfer characteristics of amorphous indium gallium zinc oxide thin film transistor (a-IGZO TFT) showed the distortion in the subthreshold region after gate bias stress, in addition to the parallel shift of threshold voltage. The capacitancevoltage (C-V) curve was also deformed from its initial shape after the gate bias stress. This study analyzes both the C-V and transfer curves plotted on the same gate voltage axis in order to investigate the mechanism driving the distortion in the transfer curve. It is deduced that an additional interfacial trap states at the bottom interface of a-IGZO are produced during gate bias stress, thereby they exhibit the back channel effect, which explains the origin of the distortion in the transfer curve and the deformation of C-V curve.
Developing a thin-film transistor with characteristics such as a large area, high mobility, and high reliability are key elements required for the next generation on displays. In this paper, we have investigated the research trends related to improving the reliability of oxide-semiconductor-based thin-film transistors, which are the primary focus of study in the field of optical displays. It has been reported that thermal treatment in a high-pressure oxygen atmosphere reduces the threshold voltage shift from -7.1 V to -1.9 V under NBIS. Additionally, a device with a SiO2/Si3N4 dual-structure has a lower threshold voltage (-0.82 V) under NBIS than a single-gate-insulator-based device (-11.6 V). The dual channel structure with different oxygen partial pressures was also confirmed to have a stable threshold voltage under NBIS. These can be considered for further study to improve the NBIS problem.
In this study, we investigated the color change of the normal light gray granite as the high value color granite. By coating the metal catalyst liquid on the surface of granite stone, the metal particles were penetrated into the granite and the color of granite was changed permanently through the annealing treatment. To increase penetration depth into the granite, we used DC (direct current) bias. Two kinds of bias were used such as DC bias and pulse DC bias. And the penetration time was changed as 30 and 60 min. In all cases, the color granite were successfully obtained. Regardless of the catalyst reaction time, the penetration depth was increased by using the bias treatment. We obtained a penetration depth of 21 mm with the DC pulse bias during 60 min.
Hydrothermal synthesis technique could be carried out for growth of ZnO nanowires atrelatively low process temperature, and it could be freely utilized with various substrates for fabricationprocess of functional electronic devices. However, it has also a demerit of relatively slow growthcharacteristics of the resulting ZnO nanowires. In this paper, an external DC bias of positive and negative0.5 [V] was applied in the hydrothermal synthesis process for 2∼8 [h] to prepare ZnO nanowires on aseed layer of AZO with high electrical conductivity. Growth characteristics of the synthesized ZnOnanowires were analyzed by FE-SEM. Material property of the grown ZnO nanowires was examined byPL analysis. The ZnO nanowires grown with positive bias revealed distinctively enhanced growthcharacteristics, and they showed a typical material property of ZnO.
In this study, a substrate-bias assisted 2-step pulse programming method is proposed for realizing 4-bit/1-cell operation of the SONOS memory. The programming voltage and time are considerably reduced by this programming method than a gate-bias assisted 2-step pulse programming method and CHEI method. It is confirmed that the difference of 4-states in the threshold voltage is maintained to more than 0.5 V at least for 10-year for the multi-level characteristics.
Analyzing electrical degradation of polycrystalline silicon transistor to applicable at several environment is very important issue. In this research, after fabricating p channel poly crystalline silicon TFT (thin film transistor) electrical characteristics were compare and analized that changed by gate bias with first measurement. As a result on and off current was reduced by variation of gate bias and especially re duce ratio of off current was reduced by 7.1×101. On/off current ratio, threshold voltage and electron mobility increased. Also, when channel length gets shorter on/off current ratio was increased more and thresh old voltage increased less. It was cause due to electron trap and de-trap to gate silicon oxide by variation of gate bias.
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