Hybrid insulators that have the advantages of both porcelain (high mechanical strength and chemical stability) as well as polymer (light weight and high resistance to pollution) insulators, can be used in place of individual porcelain and polymer insulators that are used for both mechanical support as well as electrical insulation of overhead power transmission lines. The most significant feature of hybrid insulators is the presence of porcelain/polymer interfaces where the porcelain and polymer are physically bonded. Individual porcelain and polymer insulators do not have such porcelain/polymer interfaces. Although the interface is expected to affect the mechanical/electrical properties of the hybrid insulator, systematic studies of the adhesion properties at the porcelain/polymer interface and the effect of the interface on the insulation characteristics and electric field distribution of the hybrid insulator have not been reported. In this study, we fabricated small hybrid insulator specimens with various types of interfaces and investigated the effect of the porcelain/polymer interface on the microstructure, insulating characteristics, and electric field distribution of the hybrid insulators. It was observed that the porcelain/polymer interface of the hybrid insulator does not have a significant effect on the insulating characteristics and electric field distribution, and the hybrid insulator can exhibit electrical insulating properties that are similar or superior to those of individual porcelain and polymer insulators.

In this paper, we investigated the hot carrier reliability of two kinds of device with low threshold voltage (LVT) and regular threshold voltage (RVT) in 65 nm CMOS technology. Contrary to the previous report that devices beyond 0.18 μm CMOS technology is dominated by channel hot carrier(CHC) stress rather than drain avalanche hot carrier(DAHC) stress, both of LVT and RVT devices showed that their degradation is dominated by DAHC stress. It is also shown that in case of LVT devices, contribution of interface trap generation to the device degradation is greater under DAHC stress than CHC stress, while there is little difference for RVT devices.

We have investigated the effect of electrical properties of amorphous InGaZnO thin filmtransistors (a-IGZO TFTs) by post thermal annealing in O2 ambient.The post-annealed in O2 ambienta-IGZOTFT is found to be more stable to be used for oxide-based TFT devices, and has betterperformance, such as the on/off current ratios, sub-threshold voltage gate swing, and, as well asreasonable threshold voltage, than others do. The interface trap density is controlled to achieve theoptimum value of TFT transfer and output characteristics. The device performance is significantlyaffected by adjusting the annealing condition. This effect is closely related with the modulation annealingmethod by reducing the localized trapping carriers and defect centers at the interface or in the channellayer.

The front electrode should be used to make solar cell panel so as to collect electron. The front electrode is used by paste type, printed on the Si-solar cell wafer and sintered at about 800℃. The paste is composed Ag powder and glass frit which make the ohmic contact between Ag electrode and n-type semiconductor layer. From the previous study, the Ag electrodes which used two commercial glass frit of Bi-system were so different on the interface resistance. The main composition of them was Bi-Zn-B-Si-O and few additives added in one of them. In this study, glass frit was made with the ratio of Bi2O3 and ZnO on the main composition, and then paste using glass frit was prepared respectively. And, also, the paste using the glass frit added oxide additives were prepared. The change of interface resistance was not large with the ratio of Bi2O3 and ZnO. In the case of G6 glass frit, 78 wt% Bi2O3 addition, the interface resistance was 190 Ω and most low. In the glass frit added oxide, the case of Ca increased over 10 times than it of G6 glass frit on the interface resistance. It was thaught that after sintering, Ca added glass frit was not flowed to the interface between Ag electrode and wafer but was in the Ag electrode.

Dye-sensitized solar cells (DSSCs) based on titanium dioxide (TiO2) have been extensively studied because of their promising low-cost alternatives to conventional semiconductor based solar cells. DSSCs consist of molecular dye at the interface between a liquid electrolyte and a mesoporous wide-bandgap semiconductor oxide. Most efforts for high conversion efficiencies have focused on dye and liquid electrolytes. However, interface engineering between dye and electrode is also important to reduce recombination and improve efficiency. In this work, for interface engineering, we deposited semiconducting ferroelectric BiFeO3 with bandgap of 2.8 eV on TiO2 nanoparticles and nanotubes. Photovoltaic properties of DSSCs were characterized as a function of thickness of BiFeO3. We showed that ferroelectric BiFeO3-coated TiO2 electrodes enable to increase overall efficiency of DSSCs, which was associated with efficient electron transport due to internal electric field originating from electric polarization. It was suggested that engineering the dye-TiO2 interface using ferroelectric materials as inorganic modifiers can be key parameter for enhanced photovoltaic performance of the cell.

Transparent thin film transistors (TTFT) were fabricated using the rf magnetron sputtered ZnO-SnO2 films as active layers. A ceramic target whose Zn atomic ratio to Sn is 2:1 was employed for the deposition of ZnO-SnO2 films. To study the post-annealing effects on the properties of TTFT, ZnO-SnO2 films were annealed at 200℃ or 400℃ for 5 min before In deposition for source and drain electrodes. Oxygen was added into chamber during sputtering to raise the resistivity of ZnO-SnO2 films. The effects of oxygen addition on the properties of TTFT were also investigated. 100 nm Si3N4 film grown on 100 nm SiO2 film was used as gate dielectrics. The mobility, Ion/Ioff, interface state density etc. were obtained from the transfer characteristics of ZnO-SnO2 TTFTs.

In this paper, flicker noise characteristic and channel hot carrier degradation of NMOSFETs with plasma nitrided oixde (PNO) and thermally nitrided oxide (TNO) are analyzed in depth. Compared with NMOSFET with TNO, flicker noise characteristic of NMOSFET with PNO is improved significantly because nitrogen density in PNO near the Si/SiO2 interface is less than that in TNO. However, device degradation of NMOSFET with PNO by channel hot carrier stress is greater than that with TNO although PMOSFET with PNO showed greater immunity to NBTI degradation than that with TNO in previous study. Therefore, concurrent investigation of the reliability as well as low frequency noise characteristics of NMOSFET and PMOSFET is required for the development of high performance analog MOSFET technology.

In this paper, we investigated an anomalous hump phenomenon under the positive bias stress in p-type LTPS TFTs. The devices with inferior electrical performance also show larger hump phenomenon. which can be explained by the sub-channel induced from trapped electrons under thinner gate oxide region. We can confirm that the devices with larger hump have larger interface trap density (Dit) and grain boundary trap density (Ntrap) extracted by low-high frequency capacitance method and Levinson-Proano method, respectively. From the C-V with I-V transfer characteristics, the trapped electrons causing hump seem to be generated particularly from the S/D and gate overlapped region. Based on these analysis, the major cause of an anomalous hump phenomenon under the positive bias stress in p-type poly-Si TFTs is explained by the GIDL occurring in the S/D and gate overlapped region and the traps existing in the channel edge region where the gate oxide becomes thinner, which can be inferred by the fact that the magnitude of the hump is dependent on the average trap densities.

This paper is studied for the improvement of the characteristics of gate oxide with 3-nm-thick gate oxide by deuterium ion implantation methode. Deuterium ions were implanted to account for the topography of the overlaying layers and placing the D peak at the top of gate oxide. A short anneal at forming gas to nitrogen was performed to remove the damage of D-implantation. We simulated the deuterium ion implantation to find the optimum condition by SRIM (stopping and range of ions in matter) tool. We got the optimum condition by the results of simulation. We compare the electrical characteristics of the optimum condition with others terms. We also analyzed the electrical characteristics to change the annealing conditions after deuterium ion implantation. The results of the analysis, the breakdown time of the gate oxide was prolonged in the optimum condition. And a variety of annealing, we realized the dielectric property that annealing is good at longer time. However, the high temperature is bad because of thermal stress.

We report on the formation mechanism of large Schottky barrier height (SBH) of nonalloyed Cr Schottky contacts on strained Al0.25Ga0.75N/GaN. Based on the current-voltage (I-V) and capacitance-voltage (C-V) data, the SBHs are determined to be 1.98 (±0.02) and 2.07 (±0.02) eV from the thermionic field emission and two-dimensional electron gas (2DEG) calculations, respectively. Possible formation mechanism of large SBH will be described in terms of the formation of Cr-O chemical bonding at the interface between Cr and AlGaN/GaN, low binding-energy shift to surface Fermi level, and the reduction of 2DEG electrons.

Silicon carbide (SiC)-based gas sensors can be operated at very high temperatures. So far, catalytic metal-schottky diodes respond fast to a change between a reducing and an oxidizing atmosphere. Therefore SiC diodes have been suggested for high temperature gas sensor applications. In this work, the effect of reactivity of the catalytic surface on the 4H-SiC sensor-structures in 375 K∼775 K have been studied and some fundamental simulations have also been performed.